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ksz8841-pmql single-port ethernet mac controller with pci interface rev.1.5 linkmd is a registered trademark of micrel, inc magic packet is a trademark of advanced micro devices, inc. product/application names used in this datas heet are for identification purposes only and may be trademarks of their respective companies. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com october 2007 m9999-100407-1. 5 general description the ksz8841-series single-port chip includes pci and non-pci cpu interfaces. this datasheet describes the ksz8841-pmql with pci cpu interface chips. for information on the ksz8841 non-pci cpu interface chips, refer to the ksz8841-mql datasheet. the ksz8841-pmql is a single port fast ethernet mac chip with a 32-bit/33mhz pci processor interface. designed to be fu lly compliant with the ieee 802.3u standard, the ksz8841-pmql is also available in an industrial temperature-grade version of the ksz8841- pmql, the KSZ8841-PMQLI. (see ordering information). physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower power consumption. the ksz8841-pmql is designed using a low-power cmos process that features a single 3.3v power supply with 5v tolerant i/o. linkmd ? the ksz8841-pmql is a mixed signal analog/digital device offering wake-on-lan technology. its extensive feature set includes management information base (mib) counters and cpu control/data interfaces. the ksz8841-pmql includes a unique cable diagnostics feature called linkmd ? . this feature calculates the length of the cabling plant and det ermines if there is an open/short condition in the cable. accompanying software allows the cable length and cable conditions to be conveniently displayed. in addition, the ksz8841- pmql supports hewlett pa ckard (hp) auto-mdix thereby eliminating the need to differentiate between straight or crossover cables in applications. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . functional diagram figure 1. ksz8841-pmql function diagram
micrel, inc. ksz8841-pmql october 2007 2 m9999-100407-1.5 features ? fully compliant with the ieee802.3u standard ? supports 10/100base-t/tx ? supports ieee 802.3x full-dupl ex flow control and half- duplex backpressure collision flow control ? supports burst data transfers ? 8kb internal memory for rx/tx fifo buffers ? early tx/rx functions to minimize latency through the device ? serial eeprom configuration ? single 25mhz reference clock for both phy and mac network features ? fully integrated to comply with ieee802.3u standards ? 10base-t and 100base-tx physical layer support ? auto-negotiation: 10/100mbps full and half duplex ? supports ieee 802.1q multiple vlan tagging ? on-chip wave shaping ? no external filters required ? adaptive equalizer ? baseline wander correction power modes, packaging, and power supplies ? single power supply (3.3v) with 5v tolerant i/o buffers ? enhanced power management feature with power down feature to ensure low power dissipation during device idle periods ? comprehensive led indicator support for link, activity, full/half duplex, and 10/100 speed (4 leds) ? low power cmos design ? commercial temperature range: 0 o c to +70 o c ? industrial temperature range: ?40 o c to +85 o c (KSZ8841-PMQLI) ? available in 128-pin pqfp additional features ? single chip ethernet co ntroller with ieee 802.3u support ? 32 bit/33mhz pci bus for different host processor interfaces ? dynamic buffer memory scheme ? essential for applications such as video over ip where image jitter is unacceptable ? micrel linkmd ? cable diagnostic capabilities to determine cable length and distance to fault, and to diagnose faulty cables ? wake-on-lan technology ? incorporates magic packet?, network link state, and wake-up frame technology ? hp auto mdix crossover with disable and enable option ? enhanced power management feature with power- down feature applications ? video distribution systems ? high-end cable, satellite, and ip set-top boxes ? video over ip ? voice over ip (voip) and analog telephone adapters (ata) markets ? fast ethernet ? embedded ethernet ? industrial ethernet ordering information part number junction temp. range package ksz8841-pmql 0 o c to 70 o c 128-pin pqfp KSZ8841-PMQLI ?40 o c to +85 o c 128-pin pqfp
micrel, inc. ksz8841-pmql october 2007 3 m9999-100407-1.5 revision history revision date summary of changes 1.0 09/29/05 data sheet created. 1.1 01/13/06 used detail package information. 1.2 06/12/06 corrected mrfce field for mdrxc register. the nc pin 13 was changed from ipu to ?. the pwrdn pin 36 was changed from i to ipu. 1.3 02/16/07 update support transformer and other. 1.4 06/01/07 add the package thermal in formation in the operating ratings. 1.5 10/02/07 in vddco pin description, add 100 ohm resistor for internal ldo application.
micrel, inc. ksz8841-pmql october 2007 4 m9999-100407-1.5 contents pin confi guration .............................................................................................................. ................................................ 8 pin descr iption ................................................................................................................ .................................................. 9 functional d escripti on ......................................................................................................... .......................................... 14 pci bus inte rface unit ......................................................................................................... ......................................... 14 pci bus in terface .............................................................................................................. ................................... 14 txdma logic and tx buffer ma nager .............................................................................................. .................. 14 rxdma logic and rx buffer m anager.............................................................................................. .................. 14 power mana gement............................................................................................................... ....................................... 14 power down..................................................................................................................... ..................................... 14 wake-on- lan.................................................................................................................... ................................... 14 link ch ange .................................................................................................................... ..................................... 15 wake-up packet ................................................................................................................. .................................. 15 magic packet................................................................................................................... ..................................... 15 physical layer tr ansceiver (phy) ............................................................................................... .................................. 16 100base-tx tr ansmit............................................................................................................ ...................................... 16 100base-tx re ceive............................................................................................................. ...................................... 16 pll clock synthesizer (recovery) ............................................................................................... ................................ 16 scrambler/de-scrambler (100base-tx only)....................................................................................... ....................... 16 10base-t tr ansmit .............................................................................................................. ........................................ 16 10base-t re ceive ............................................................................................................... ........................................ 16 mdi/mdi-x auto crossover ....................................................................................................... ................................... 17 straight cable................................................................................................................. ...................................... 17 crossover cable................................................................................................................ ................................... 18 auto nego tiation ............................................................................................................... ............................................ 18 linkmd cable diagnostics ....................................................................................................... ...................................... 20 access......................................................................................................................... .................................................. 20 usage.......................................................................................................................... .................................................. 20 media access control (mac) and other........................................................................................... ............................. 20 inter packet gap (i pg) ......................................................................................................... ........................................ 20 back-off al gorithm............................................................................................................. ........................................... 20 late collision ................................................................................................................. ............................................... 20 flow c ontrol................................................................................................................... ............................................... 20 half-duplex ba ckpressure ....................................................................................................... ..................................... 21 clock generator................................................................................................................ ............................................ 21 eeprom interface ............................................................................................................... ........................................ 21 loopback su pport............................................................................................................... .......................................... 23 host comm unicatio n ............................................................................................................. ......................................... 24 host communication descripto r lists and data buffers ........................................................................... ................... 24 receive descriptors (rdes0-rdes3) .............................................................................................. ........................... 24 transmit descriptor s (tdes0-tdes3)............................................................................................. ............................ 26 pci configurati on registers .................................................................................................... ...................................... 28 configuration id regist er (cfid offset 00h) .................................................................................... ........................... 29 command and status configuration register (cfcs offset 04h).................................................................... ........... 29 configuration revision regi ster (cfrv o ffset 08h).............................................................................. ...................... 31 configuration latency timer r egister (cflt offset 0ch)......................................................................... .................. 31 configuration base memory addres s register (cbm a offset 10h) ................................................................... ......... 31 subsystem id register (csid offset 2ch) ........................................................................................ .......................... 32 capabilities pointer regist er (ccap o ffset 34h)................................................................................ ......................... 32 configuration interrupt regi ster (cfit of fset 3ch) ............................................................................. ........................ 32 capabilities id register (ccid offs et 50h)..................................................................................... ............................. 33 power-management control and status register (cpmc offset 54h)................................................................. ....... 35 pci control & stat us registers ................................................................................................. .................................... 36 mac dma transmit control regist er (mdtxc o ffset 0x0000) ........................................................................ ........... 36 mac dma receive control regist er (mdrxc o ffset 0x0004)......................................................................... ........... 37
micrel, inc. ksz8841-pmql october 2007 5 m9999-100407-1.5 mac dma transmit start command regi ster (mdtsc o ffset 0x0008) .................................................................. ... 38 mac dma receive start command r egister (mdrsc o ffset 0x 000c) ................................................................... .. 39 transmit descriptor list base ad dress register (t dlb offset 0x0010)............................................................ .......... 39 receive descriptor list base addr ess register (rdl b offset 0x0014) ............................................................. ......... 39 mac multicast table 0 regist er (mtr0 offs et 0x0020) ............................................................................ .................. 39 mac multicast table 1 regist er (mtr1 offs et 0x0024) ............................................................................ .................. 40 interrupt enable register (inten offs et 0x0028) ................................................................................ ........................ 40 interrupt status register (intst offs et 0x002c) ................................................................................ ......................... 41 mac additional station addres s low register (maal0-15) ......................................................................... ............... 42 mac additional station addres s high register (maah0-15)........................................................................ ............... 42 mac/phy and cont rol registers .................................................................................................. ................................. 43 mac address register low (0x0200): marl ........................................................................................ ...................... 43 mac address register middle (0x020 2): marm ..................................................................................... .................... 44 mac address register high (0x0204 ): marh ....................................................................................... ...................... 44 on-chip bus control regist er (offset 0x 0210): obcr............................................................................. ................... 44 eeprom control register (offset 0x02 12): eepcr................................................................................. .................. 44 memory bist info regist er (offset 0x 0214): mbir ................................................................................ ..................... 45 global reset register (offset 0x021 6): grr..................................................................................... .......................... 45 power management capabilities regi ster (offset 0x0218): pmcr ................................................................... .......... 46 wakeup frame control regist er (offset 0x 021a): wfcr ............................................................................ ............... 47 wakeup frame 0 crc0 register (offset 0x022 0): wf0crc0.......................................................................... .......... 48 wakeup frame 0 crc1 register (offset 0x022 2): wf0crc1.......................................................................... .......... 48 wakeup frame 0 byte mask 0 re gister (offset 0x0224): wf0bm0 .................................................................... ........ 48 wakeup frame 0 byte mask 1 re gister (offset 0x0226): wf0bm1 .................................................................... ........ 48 wakeup frame 0 byte mask 2 re gister (offset 0x0228): wf0bm2 .................................................................... ........ 48 wakeup frame 0 byte mask 3 regi ster (offset 0x 022a): wf0bm3 .................................................................... ....... 49 wakeup frame 1 crc0 register (offset 0x023 0): wf1crc0.......................................................................... .......... 49 wakeup frame 1 crc1 register (offset 0x023 2): wf1crc1.......................................................................... .......... 49 wakeup frame 1 byte mask 0 re gister (offset 0x0234): wf1bm0 .................................................................... ........ 49 wakeup frame 1 byte mask 1 re gister (offset 0x0236): wf1bm1 .................................................................... ........ 49 wakeup frame 1 byte mask 2 re gister (offset 0x0238): wf1bm2 .................................................................... ........ 50 wakeup frame 1 byte mask 3 regi ster (offset 0x 023a): wf1bm3 .................................................................... ....... 50 wakeup frame 2 crc0 register (offset 0x024 0): wf2crc0.......................................................................... .......... 50 wakeup frame 2 crc1 register (offset 0x024 2): wf2crc1.......................................................................... .......... 50 wakeup frame 2 byte mask 0 re gister (offset 0x0244): wf2bm0 .................................................................... ........ 50 wakeup frame 2 byte mask 1 re gister (offset 0x0246): wf2bm1 .................................................................... ........ 51 wakeup frame 2 byte mask 2 re gister (offset 0x0248): wf2bm2 .................................................................... ........ 51 wakeup frame 2 byte mask 3 regi ster (offset 0x 024a): wf2bm3 .................................................................... ....... 51 wakeup frame 3 crc0 register (offset 0x025 0): wf3crc0.......................................................................... .......... 51 wakeup frame 3 crc1 register (offset 0x025 2): wf3crc1.......................................................................... .......... 51 wakeup frame 3 byte mask 0 re gister (offset 0x0254): wf3bm0 .................................................................... ........ 52 wakeup frame 3 byte mask 1 re gister (offset 0x0256): wf3bm1 .................................................................... ........ 52 wakeup frame 3 byte mask 2 re gister (offset 0x0258): wf3bm2 .................................................................... ........ 52 wakeup frame 3 byte mask 3 regi ster (offset 0x 025a): wf3bm3 .................................................................... ....... 52 chip id and enable register (offset 0x0400 ): ci der ............................................................................. .................... 52 chip global control regist er (offset 0x 040a): cgcr ............................................................................. .................... 53 indirect access control regi ster (offset 0x04a0): iacr ......................................................................... .................... 53 indirect access data register 1 (offset 0x 04a2): iadr1 ......................................................................... ................... 54 indirect access data register 2 (offset 0x 04a4): iadr2 ......................................................................... ................... 54 indirect access data register 3 (offset 0x 04a6): iadr3 ......................................................................... ................... 54 indirect access data register 4 (offset 0x 04a8): iadr4 ......................................................................... ................... 54 indirect access data regist er 5 (offset 0x04aa): iadr5 ......................................................................... ................... 54 reserved (offset 0x04c0-0x 04cf) ................................................................................................ .............................. 54 phy 1 mii register basic control register (offset 0x04d0): p1mbcr .............................................................. ........ 55 phy 1 mii register basic status re gister (offset 0x 04d2): p1mbsr ............................................................... ......... 56
micrel, inc. ksz8841-pmql october 2007 6 m9999-100407-1.5 phy 1 phyid low register (offset 0x04d4) : phy1ilr.............................................................................. ................ 56 phy 1 phyid high register (offset 0x04d6) : phy1ihr ............................................................................. ............... 57 phy 1 auto-negotiation advertisement register (offset 0x04d8): p1anar .......................................................... .... 57 phy 1 auto-negotiation link partner abilit y register (offset 0x04da): p1 anlpr.................................................. ... 57 phy1 linkmd control/status (offset 0x04f 0): p1vct.............................................................................. .................. 58 phy1 special control/status regi ster (offset 0x04f 2): p1phyctrl................................................................ ........ 58 reserved (offset 0x04f8 - 0x04fa).............................................................................................. ............................... 59 port 1 phy special control/status, linkmd (offset 0x 0510): p1 scslmd ............................................................ ..... 59 port 1 control register 4 (offset 0x051 2): p1cr4............................................................................... ........................ 60 port 1 status register (offset 0x 0514): p1sr ................................................................................... .......................... 61 reserved (offset 0x0516 ? 0x 0560).............................................................................................. ............................... 62 mib (management inform ation base) counters..................................................................................... ...................... 63 example: mib counter read (read ?rx64octets? counter at indi rect address offs et 0x0e) ........................................ 64 additional mib informat ion..................................................................................................... ....................................... 64 absolute maximum ratings (1) ............................................................................................................................... ......... 65 operating ratings (2) ............................................................................................................................... ......................... 65 electrical characteristics (4) ............................................................................................................................... ............. 65 timing di agrams ................................................................................................................ ............................................. 67 eeprom ti ming.................................................................................................................. ......................................... 67 auto negotiat ion ti ming........................................................................................................ ........................................ 68 reset timing................................................................................................................... .............................................. 69 selection of isolat ion transf ormers............................................................................................ .................................. 70 selection of refe rence crystal ................................................................................................. ..................................... 70 package info rmation ............................................................................................................ ........................................... 71 acronyms a nd glo ssary.......................................................................................................... ....................................... 72
micrel, inc. ksz8841-pmql october 2007 7 m9999-100407-1.5 list of figures figure 1. ksz8841-pmq l function diagram ....................................................................................... ............................. 1 figure 2. ksz8841-pmql 128-pin pqfp (top vi ew)................................................................................ ....................... 8 figure 3. typical stra ight cable connection ................................................................................... ................................ 17 figure 4. typical cros sover cable connection .................................................................................. ............................. 18 figure 5. auto negotiatio n and parallel operation ............................................................................. ............................. 19 figure 6. port 1 near-end (remote) loo pback path.............................................................................. ......................... 23 figure 7. eeprom read cycle timing diagram .................................................................................... ........................ 67 figure 8. auto-n egotiation timing ............................................................................................. ...................................... 68 figure 9. re set timing ........................................................................................................ ............................................. 69 figure 10. 128-pi n pqfp package............................................................................................... ................................... 71 list of tables table 1. mdi/mdi- x pin defi nitions ............................................................................................ ..................................... 17 table 2. ksz8841-p mql eeprom format........................................................................................... ......................... 21 table 3. ksz8841-pmql conf igparam in eepr om fo rmat............................................................................ .............. 23 table 4. format of port mib counters .......................................................................................... ................................... 63 table 5. port 1?s mib counte rs indirect me mory offsets........................................................................ ......................... 64 table 6. eeprom ti ming parameters ............................................................................................. ............................... 67 table 7. auto nego tiation pa rameters .......................................................................................... ................................... 68 table 8. reset timing para meters .............................................................................................. .................................... 69 table 9. transforme r selection criteria ....................................................................................... .................................... 70 table 10. qualified si ngle port magnetics ...................................................................................... .................................. 70 table 11. typical reference crystal characteristics ............................................................................ ............................ 70
micrel, inc. ksz8841-pmql october 2007 8 m9999-100407-1.5 pin configuration n d r w p d n g a a d d v d n g d 3 3 4 3 5 3 6 3 7 3 8 3 ksz8841-pmql vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddar x nc nc agnd nc nc vdda agnd agnd nc nc agnd vddap 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 agnd 6 2 d a p 8 2 d a p 7 2 d a p n 2 e b c c n c n n r r e p n q e r l e s d i n y d r t n e m a r f r a p n t s r 2 x 9 2 d a p 0 3 d a p c d d v d n g d 1 3 d a p n 0 e b c n 1 e b c n 3 e b c c n c n n r r e s o i d d v d n g d n t n g n l e s v e d n p o t s n y d r i 1 x 6 9 5 9 4 9 3 9 2 9 1 9 0 9 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 8 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 9 6 8 6 7 6 6 6 5 6 1 2 d a p 2 2 d a p 3 2 d a p 4 2 d a p 5 2 d a p 1 0 1 0 0 1 9 9 8 9 7 9 pad20 2 0 1 103 n e n a c s pad17 n e t s e t pad0 pad1 pad2 vddio dgnd pad3 pad4 pad5 pad6 pad7 pad8 pad9 pad10 pad11 pad12 pad13 pad14 pad15 pad16 vddio dgnd pad18 pad19 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 2 d e l 1 p 1 d e l 1 p 0 d e l 1 p c n c n c n d n g d o i d d v c n c n c n c n k s e e c n o i d d v d n g d k l c p c n n e m p c n n r t n i c n c n s c e e c n d n g d o c d d v n e e e 3 d e l 1 p o d e e i d e e o i d d v 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 3 1 3 2 3 dgnd o i d d v figure 2. ksz8841-pmql 128-pin pqfp (top view)
micrel, inc. ksz8841-pmql october 2007 9 m9999-100407-1.5 pin description pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin to ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin to ground. 3 4 5 p1led2 p1led1 p1led0 opu opu opu port 1 led indicators 1 defined as follows: leds turn on when low. chip global control register: cgcr bit [15,9] [0,0] default [0,1] p1led3 2 ? ? p1led2 link/act 100link/act p1led1 full duplex/col 10link/act p1led0 speed full duplex reg. cgcr bit [15,9] [1,0] [1,1] p1led3 2 act ? p1led2 link ? p1led1 full duplex/col ? p1led0 speed ? notes : 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. 6 nc ? no connect 7 nc ? no connect 8 nc ? no connect 9 dgnd gnd digital ground 10 vddio p 3.3v digital i/o v dd 11 nc ? no connect 12 pclk ipd pci bus clock this clock provides the timing for all pci bus phases. the rising edge defines the start of each phase. the clock maximum frequency is 33mhz. 13 nc ? no connect 14 pmen opu power management enable asserted low. when asserted, this signal indicates that a wake-on-lan packet has been received in this ethernet mac chip. 15 nc ? no connect 16 intrn opd interrupt request
micrel, inc. ksz8841-pmql october 2007 10 m9999-100407-1.5 pin number pin name type pin function active low signal to host cpu to request an interrupt when any one of the interrupt conditions occurs in the registers. this pin should be pull-up externally. 17 nc ? no connect 18 nc ? no connect 19 eecs opu eeprom chip select this signal is used to select an external eeprom device 20 nc ? no connect 21 nc ? no connect 22 nc ? no connect 23 dgnd gnd digital ground 24 vddco p 1.2v core voltage output. (internal 1.2v ldo power supply output) this pin provides 1.2v power supply to all 1.2v power pin, vddc, vdda, vddap. it is recommended the pin should be connected to 3.3v power rail by a 100ohm resistor for the internal ldo application. 25 nc ? no connect 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock 4 s serial clock to load configuration data from the serial eeprom. 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom. 31 nc ? no connect 32 vddio p 3.3v digital i/o v dd . 33 vddio p 3.3v digital i/o v dd . 34 dgnd gnd digital ground 35 dgnd gnd digital ground 36 pwrdn ipu full-chip power-down input. active low. 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd 39 agnd gnd analog ground 40 nc ? no connect 41 nc ? no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd 44 nc ? no connect
micrel, inc. ksz8841-pmql october 2007 11 m9999-100407-1.5 pin number pin name type pin function 45 rxp1 i/o physical receive (mdi) or transmit (mdix)signal (+ differential) 46 rxm1 i/o physical receive (mdi) or transmit (mdix) signal (? differential) 47 agnd gnd analog ground 48 txp1 i/o physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o physical transmit (mdi) or receive (mdix) signal (? differential) 50 vddatx p 3.3v analog v dd 51 vddarx p 3.3v analog v dd 52 nc ? no connect 53 nc ? no connect 54 agnd gnd analog ground 55 nc ? no connect 56 nc ? no connect 57 vdda p 1.2 analog v dd 58 agnd gnd analog ground 59 nc ? no connect 60 nc ? no connect 61 iset o set physical transmit output current pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground 63 vddap p 1.2v analog v dd for pll 64 agnd gnd analog ground 65 x1 i 66 x2 o 25mhz crystal/oscillato r clock connections pins (x1, x2) connect to a crystal. if an os cillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is no connected. note: clock is 50ppm for both crystal and oscillator. 67 rstn ipu hardware reset, active low rstn will cause the ksz8841-pmql to reset all of its functional blocks. rstn must be asserted for a minimum duration of 10 ms. 68 par i/o pci parity even parity computed for pad[31:0] and cbe[ 3:0]n, master drives par for address and write data phase, target drives par for read data phase. 69 framen i/o pci cycle frame this signal is asserted low to indicate t he beginning of the address phase of the bus transaction and de-asserted before the fi nal transfer of the data phase of the transaction in a bus master mode. as a targ et, the device monitors this signal before decoding the address to check if the cu rrent transaction is addressed to it. 70 irdyn i/o pci initiator ready as a bus master, this signal is asserted lo w to indicate valid data phases on pad[31:0] during write data phases, indicates it is read y to accept data during read data phases. as a target, it?ll monitor this irdyn signal that indicates the master has put the data on the bus. 71 trdyn i/o pci target ready as a bus target, this signal is asserted low to indicate valid data phases on pad[31:0] during read data phases, indicates it is r eady to accept data during write data phases. as a master, it will monitor this trdyn signal that indicates the ta rget is ready for data
micrel, inc. ksz8841-pmql october 2007 12 m9999-100407-1.5 pin number pin name type pin function during read/write operation. 72 stopn i/o pci stop this signal is asserted low by the target dev ice to request the master device to stop the current transaction. 73 idsel i/o pci initialization device select this signal is used to select the ksz8841- pmql during configuration read and write transactions. active high. 74 devseln i/o pci device select this signal is asserted low when it is selected as a target during a bus transaction. as a bus master, the ksz8841-pmql samples this signal to insure that a pci target recognizes the destination ad dress for the data transfer. 75 reqn o pci bus request the ksz8841-pmql will assert this signal low to request pci bus master operation. 76 gntn i pci bus grant this signal is asserted low to indicate to the ksz8841-pmql that it has been granted the pci bus master operation. 77 perrn i/o pci parity error the ksz8841-pmql as a master or target will assert this signal low to indicate a parity error on any incoming data. as a bus master, it will monitor this signal on all write operations. 78 dgnd gnd digital ground 79 vddio p 3.3v digital i/o v dd 80 serrn o pci system error this system error signal is asserted low by the ksz8841-pmql. this signal is used to report address parity errors. 81 nc ? no connect 82 nc ? no connect 83 nc ? no connect 84 nc ? no connect 85 cbe3n i/o 86 cbe2n i/o 87 cbe1n i/o 88 cbe0n i/o command and byte enable these signals are multiplexed on the same pci pins. during the address phase, these lines define the bus command. during the data phase, these lines are used as byte enables, the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. 89 pad31 i/o pci address / data 31 address and data are multiplexed on the al l of the pad pins. the pad pins carry the physical address during the first clock cyc le of a transaction, and carry data during the subsequent clock cycles. 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd 92 vddio p 3.3v digital i/o v dd 93 pad30 i/o pci address / data 30 94 pad29 i/o pci address / data 29 95 pad28 i/o pci address / data 28 96 pad27 i/o pci address / data 27
micrel, inc. ksz8841-pmql october 2007 13 m9999-100407-1.5 pin number pin name type pin function 97 pad26 i/o pci address / data 26 98 pad25 i/o pci address / data 25 99 pad24 i/o pci address / data 24 100 pad23 i/o pci address / data 23 101 pad22 i/o pci address / data 22 102 pad21 i/o pci address / data 21 103 pad20 i/o pci address / data 20 104 pad19 i/o pci address / data 19 105 pad18 i/o pci address / data 18 106 pad17 i/o pci address / data 17 107 dgnd gnd digital ground 108 vddio p 3.3v digital i/o v dd 109 pad16 i/o pci address / data 16 110 pad15 i/o pci address / data 15 111 pad14 i/o pci address / data 14 112 pad13 i/o pci address / data 13 113 pad12 i/o pci address / data 12 114 pad11 i/o pci address / data 11 115 pad10 i/o pci address / data 10 116 pad9 i/o pci address / data 9 117 pad8 i/o pci address / data 8 118 pad7 i/o pci address / data 7 119 pad6 i/o pci address / data 6 120 pad5 i/o pci address / data 5 121 pad4 i/o pci address / data 4 122 pad3 i/o pci address / data 3 123 dgnd gnd digital ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital i/o v dd 126 pad2 i/o pci address / data 2 127 pad1 i/o pci address / data 1 128 pad0 i/o pci address / data 0 notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipd = input with internal pull-down. ipu = input with internal pull-up. opd = output with internal pull-down. opu = output with internal pull-up.
micrel, inc. ksz8841-pmql october 2007 14 m9999-100407-1.5 functional description the ksz8841-pmql is a single chip fast ethernet mac cont roller consisting of a 10/100 physical layer transceiver (phy), a mac, and a pci interface unit that controls the ksz8841-pmql via a 32 bit/33mhz pci processor interface. the ksz8841-pmql is fully compliant to the ieee802.3u standard. pci bus interface unit pci bus interface the pci bus interface implements pci v2.2 bus protocols and configuration space. the ksz8841-pmql supports bus master reads and writes to cpu memory, and cpu access to on-chip register space. wh en the cpu reads and writes the configuration registers of the ksz 8841-pmql, it is as a slave. so the ksz8841-pmql can be either a pci bus master or slave. the pci bus interface is also responsibl e for managing the dma interfaces and the host processors access. arbitration logic within the pci bus interface unit accepts bus requests from the txdma logic and rxdma logic. the pci bus interface also manages interrupt generation for a host processor. txdma logic and tx buffer manager the ksz8841-pmql supports a multi-frame, multi-fragment dma gather process. descriptors representing frames are built and linked in system memory by a host processor. th e txdma logic is responsible for transferring the multi- fragment frame data from the host memory into the tx buffer. the ksz8841-pmql uses 4k bytes of transmit data buffer between the txdma logic and transmit mac. when the txdma logic determines there is enough space available in the tx buffer, the txdma logic will move any pending frame data into the tx buffer. the management me chanism depends on the transmit descriptor list. rxdma logic and rx buffer manager the ksz8841-pmql supports a multi-frame, multi-fragment dm a scatter process. descriptors representing frames are built and linked in system memory by t he host processor. the rxdma logic is responsible for transferring the frame data from the rx buffer to the host memory. the ksz8841-pmql uses 4k bytes of receive data buffer between the receive mac and rxdma logic. the management mechanism depends on the receive descriptor list. power management power down the ksz8841-pmql features a port power-down mode. to save power, the user can power-d own this port that is not in use by setting bit 11 in either p1cr4 or p1mbcr register for this port. to bring the port back up, reset bit 11 in these registers. in addition, there is a full chip power-down mode by pulled- down the pwrdn pin 36. when this pin is pulled-down, the entire chip powers down. transitioning this pin from pu ll-down to pull-up results in a power up and chip reset. wake-on-lan wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. examples of meaningful data in clude the reception of a magic packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. in all of t hese instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. a wake-up event is a request for hardware and/or software ex ternal to the network device to put the system into a powered state (working).
micrel, inc. ksz8841-pmql october 2007 15 m9999-100407-1.5 a wake-up signal is caused by: 1. detection of a change in the network link state 2. receipt of a network wake-up frame 3. receipt of a magic packet link change link status wake events are us eful to indicate a ch ange in the network?s availability, especially when this change may impact the level at which the system sh ould re-enter the sleeping st ate. for example, a change from link off to link on may trigger the system to re-enter sleep at a higher leve l (d2 versus d3) so that wake frames can be detected. conversely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (d3 versus d2) since the network is not currently available. note : references to d0, d1, d2, and d3 are power management states defined in a similar fashion to the way they are defined for pci. for more information, refer to the pci specification at www.pcisig.com/specificat ions/conventional/pcipm1.2.pdf. wake-up packet wake-up packets are certain types of pack ets with specific crc values that a sy stem recognizes as a ?wake up? frame. the ksz8841-pmql supports up to four users defined wake-up frames as below: 1. wake-up frame 0 is defined in regist ers 0x0220-0x022a and is enabled by bit 0 in wakeup frame control register. 2. wake-up frame 1 is defined in regist ers 0x0230-0x023a and is enabled by bit 1 in wakeup frame control register. 3. wake-up frame 2 is defined in regist ers 0x0240-0x024a and is enabled by bit 2 in wakeup frame control register. 4. wake-up frame 3 is defined in regist ers 0x0250-0x025a and is enabled by bit 3 in wakeup frame control register magic packet magic packet technology is used to remotely wake up a sleeping or powered off pc on a lan. this is accomplished by sending a specific packet of information, called a magic pack et frame, to a node on the network. when a pc capable of receiving the specific frame goes to sl eep, it enables the magic packet rx mode in the lan controller, and when the lan controller receives a m agic packet frame, it will alert the system to wake up. magic packet is a standard feature integrated into the ksz8841-pmql. the chip implements multiple advanced power- down modes including magic packet to cons erve power and operate more efficiently. once the ksz8841-pmql has been put into magic packet e nable mode (wfcr[7]=1), it scans all incoming frames addressed to the node for a specific data sequence, which indi cates to the chip this is a magic packet (mp) frame. a magic packet frame must also meet the basic requirements for the lan technology chosen, such as source address (sa), destination addres s (da), which may be the receiving station?s i eee address or a multicast or broadcast address and crc. the specific sequence consists of 16 duplications of the ieee address of this node, with no breaks or interruptions. this sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. the synchronization stream allows the scanning state machine to be much simp ler. the synchronization stream is defined as 6 bytes of ffh. the device will also ac cept a broadcast frame, as long as the 16 duplications of the ieee address match the address of the machine to be awakened. example if the ieee address for a particular node on a network is 11 h 22h, 33h, 44h, 55h, 66h, the lan controller would be scanning for the data sequence (a ssuming an ethernet frame): destination source misc: ff ff ff ff ff ff - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 -11 22 33 44 55 66 - misc -crc. there are no further restrictions on a magic packet frame. for instance, the sequence could be in a tcp/ip packet or an ipx packet. the frame may be bridged or routed across the networ k without affecting its ab ility to wake-up a node at the frame?s destination if the lan controller scans a frame and does not find the spec ific sequence shown above, it discards the frame and takes no further action. if the controller (ksz8841-pmql) det ects the data sequence, however, it then alerts the pc?s power management circuitry (asserted t he pmen pin) to wake up the system.
micrel, inc. ksz8841-pmql october 2007 16 m9999-100407-1.5 physical layer transceiver (phy) 100base-tx transmit the 100base-tx transmit function performs parallel-to-serial c onversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-ser ial conversion, which converts the 25mhz 4-bit nibbles into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, follow ed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then tr ansmitted in mlt3 current output. an external 1% 3.01k ? resistor for the 1:1 transforme r ratio sets the output current. the output signal has a typical rise/fall time of 4ns and comp lies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. th e wave-shaped 10base-t output driver is also incor porated into the 100base- tx driver. 100base-tx receive the 100base-tx receiver function perf orms adaptive equalization, dc restoration, mlt3-t o-nrzi conversion, data and clock recovery, nrzi-to-nrz conver sion, de-scrambling, 4b/5b decoding, a nd serial-to-parallel conversion. the receiving side starts with the equalization filter to co mpensate for inter-symbol interf erence (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some know n cable characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from th e edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de- scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to an mii format and prov ided as the input data to the mac. pll clock synthesizer (recovery) the internal pll clock synthesizer generates 125mhz, 62 .5mhz, 41.66mhz, and 25mhz clocks by setting the on-chip bus speed control register obcr for ksz8841-pmql system timing. these internal clocks are generated from an external 25mhz crystal or oscillator. note: default setting is 25mhz in obcr register, recommend s the software driver to set it to 125mhz for best performance. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectr um of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-repetitive sequence. then the rece iver de-scrambles the inco ming data stream using the same sequence as at the transmitter. 10base-t transmit the 10base-t driver is incorporated wi th the 100base-tx driver to allow fo r transmission using the same magnetic. they are internally wave-shaped and pre-emphasized into out puts with typical 2.4v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffers and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding function. the manchester-encoded data stream is separated into cl ock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths to prevent noise at the rxp-or-rxm input from falsely triggering
micrel, inc. ksz8841-pmql october 2007 17 m9999-100407-1.5 the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8841-pmql decodes a data frame. the receiver clock is maintained active dur ing idle periods in between data reception. mdi/mdi-x auto crossover to eliminate the need for crossover cables between sim ilar devices, the ksz8841-pmql supports hp-auto mdi/mdi-x and ieee 802.3u standard mdi/mdi-x auto crosso ver. hp-auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receiv e pairs and correctly assigns tr ansmit and receive pairs for the ksz8841-pmql device. this feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configurat ion connection. the auto-crossover fe ature can be disabled through the port control registers. the ieee 802.3u standard mdi and mdi-x definitions are: mdi mdi-x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 1. mdi/mdi-x pin definitions straight cable a straight cable connects an mdi device to an mdi-x devic e or an mdi-x device to an mdi device. the following diagram shows a typical straight cable connection between a net work interface card (nic) (mdi) and a switch (mdix) or a hub (mdi-x). figure 3. typical straight cable connection
micrel, inc. ksz8841-pmql october 2007 18 m9999-100407-1.5 crossover cable a crossover cable connects an mdi device to another mdi dev ice, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connec tion between two switches or hubs (two mdi-x devices). figure 4. typical crossover cable connection auto negotiation the ksz8841-pmql conforms to the auto negotiation protocol as described by the 802.3 committee. auto negotiation allows unshielded twisted pair (utp) link pa rtners to select the best common mode of operation. in auto negotiation, the link part ners advertise capabilities ac ross the link to ea ch other. if auto negotiation is not supported or the link partner to the ksz8841-pmql is forc ed to bypass auto negotiation, the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. the link setup is shown in the following flow diagram (figure 3).
micrel, inc. ksz8841-pmql october 2007 19 m9999-100407-1.5 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles ttempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow no yes no yes figure 5. auto negotiation and parallel operation
micrel, inc. ksz8841-pmql october 2007 20 m9999-100407-1.5 linkmd cable diagnostics the ksz8841-pmql linkmd uses time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs and then analyzes the shape of the reflected signal. timing t he pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of +/?2m. access linkmd is initiated by accessing register p1vct, the linkmd control/status r egister, in conjunction with register p1cr4, the 100base-tx phy controller register. usage linkmd can be run at any time. to use linkmd, disable hp auto-mdix by writing a ?1? to p1cr4[10] to enable manual control over the pair used to transmit the linkmd pulse. t he self-clearing cable diagnostic test enable bit, p1vct[15], is set to ?1? to start the test on this pair. when bit p1vct[15] returns to ?0?, the test is complete. the test result is returned in bits p1vct[14-13] and the distance is returned in bits p1vct[8-0]. the cable diagnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed if p1vct[14-13]=11 case, this indicates an invalid test, occurs when the ksz8841-pmql is unable to shut down the link partner. in this instance, the test is not run, since it would be impossible for the ksz8841-pmql to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance (in meters) can approximat ely be determined by the following formula: distance = p1vct[8-0] x 0.4m this constant may be calibrated for different cabling conditi ons, including cables with a velocity of propagation that varies significantly from the norm. media access contro l (mac) and other the ksz8841-pmql strictly abides by ieee 802.3 standards to maxi mize compatibility. inter packet gap (ipg) if a frame is successfully transmitted, the minimum 96-bits time for ipg is between the two consec utive packets. if the current packet is experiencing collisions , the minimum 96-bits time for ipg is fr om carrier sense to the next transmit packet. back-off algorithm the ksz8841-pmql implements the ieee st andard 802.3 binary exponential back-off algorithm in half-duplex mode. after 16 collisions, the packet is dropped. late collision if a transmit packet experienc es collisions after 512 bit times of t he transmission, the packet is dropped. flow control the ksz8841-pmql supports standard 802.3x flow c ontrol frames on both transmit and receive sides. on the receive side, if t he ksz8841-pmql receives a pause control fr ame, the ksz8841-pmql will not transmit the next normal frame until the timer, specif ied in the pause control frame, expi res. if another pause frame is received before the current timer expire s, the timer will be updated wi th the new value in the second pause frame. during this period (while it is flow controll ed), only flow control packets from the ksz8841-pmql are transmitted.
micrel, inc. ksz8841-pmql october 2007 21 m9999-100407-1.5 on the transmit side, the ksz8841-pmql ha s intelligent and efficient ways to det ermine when to invoke flow control. the flow control is based on ava ilability of the sy stem reso urces. the ksz8841-pmql issues a flow contro l frame (xon), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ksz8841-pmql se nds out another flow control frame (xoff) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feat ure is provided to prevent the flow control mechanism from being co nstantly activated and deactivated. half-duplex backpressure a half-duplex backpress ure option (non-ieee 802.3 standa rds) is also provided. the activation and deactivation conditions are the same as above in full-duplex mode. if backpressure is required, the ksz8841-pmql sends preambles to defer the other stations' tr ansmission (carrier sense deference). to avoid jabber and excessive deference (as defined in th e 802.3 standard), after a certain time, the ksz8841-pmql discontinues the carrier sense and then raises it again quickly . this short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sens e deferred state. if the port has packets to send during a backpressure situation, the carrier se nse type backpressure is in terrupted and those packets are transmitted instead. if there are no additional packets to send, carrier sense type backpressure is reactivated again until chip resources free up. if a collision occurs, the binary ex ponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collidi ng and maintaining carrier sense to prevent packet reception. the backpressure will take effe ct automatically in auto-negot iation enable and half-duplex mode. clock generator the x1 and x2 pins are connected to a 25mhz crystal. x1 can also serve as the connector to the 3.3v 25mhz oscillator (as described in the pin description). eeprom interface an external serial eeprom with a standard microwire bus inte rface is used for non-volatile storage of information such as the node address and subsystem id. as part of the initialization after system reset, the ksz 8841-pmql reads the external eeprom and places the data into certain host-acce ssible registers if the eeen pin is pulled-up, the ksz8841-pmql performs an automatic read of the eeprom word from 0x0 to 0x6 after the de-a ssertion of reset. an eeprom of 1 kb(93c46) or 4kb( 93c66) can be used based on application. the eeprom read/write function can also be performed by software reading and writ ing to the eepcr register. the ksz8841-pmql eeprom format is given in table 2. word 15 8 7 0 0x0 reserved 0x1 mac address byte 2 mac address byte 1 0x2 mac address byte 4 mac address byte 3 0x3 mac address byte 6 mac address byte 5 0x4 0x5 0x6 0x7-0x3f subsystem id subsystem vendor id configparam not used by ksz8841-pmql (available for user to use) table 2. ksz8841-pmql eeprom format
micrel, inc. ksz8841-pmql october 2007 22 m9999-100407-1.5 the configparam in the eeprom format is shown below. bit name description 15 new_cap new capabilities indicates whether or not the ksz8841-pmql implements a list of new capabilities. when set, this bit indicates the presence of new capabilities. when reset, new capabilities are not implemented. the value of this bit is loaded to the new_cap bit in cfcs register. 14 no_srst no soft reset when this bit is set, indicates that ksz8841- pmql transitioning from d3_hot to d0 because of powerstate commands do not perform an internal reset. configuration context is preserved. upon transition from the d3_hot to the d0 initialized state, no additional operating system interventi on is required to preserve configuration context beyond writing the powerstate bits. when this bit is clear, ksz8841-pmql performs an internal reset upon transitioning from d3_hot to d0 via software control of the powerstate bits. configuration context is lost when perform ing the soft reset. upon transition from the d3_hot to the d0 state, full reinitia lization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transit ion from d3_hot to d0 by a system or bus segment reset will return to the dev ice state d0 uninitialized with only pme context preserved if pme is supported and enabled. this bit is loaded to bit 3 of cpmc register 13 reserved 12 pme_d2 pme -support d2 when this bit is set, the ksz8841-pmql asserts pme event when the ksz8841- pmql is in d2 state and pme_en is set. otherwise, the ksz8841-pmql does not assert pme event when the ks z8841-pmql is in d2 state. this bit is loaded to bit 13 of pmcr register, and bit 29 of ccid register. 11 pme_d1 pme support d1 when this bit is set, the k8841p asserts pme event when the k8841p is in d1 state and pme_en is set. otherwise, the ksz8841-pmql does not assert pme event when the ksz8841-pmql is in d1 state. this bit is loaded to bit 12 of pmcr register, and bit 28 of ccid register. 10 d2_sup d2 support when this bit is set, the ksz8841-pm ql supports d2 power state. this bit is loaded to bit 10 of pmcr register, and bit 26 of ccid register. 9 d1_sup d1 support when this bit is set, the ksz8841-pm ql supports d1 power state. this bit is loaded to bit 9 of pmcr register, and bit 25 of ccid register. 8 - 6 reserved 5 dsi device specific initialization this bit indicates whether special initializat ion of this function is required (beyond the standard pci configuration header) befor e the generic class device driver is able to use it. a ?1? indicates that the function requires a device specific initialization sequence following transition to the d0 uninitialized st ate. this bit is loaded to bit 5 of pmcr register and bit 21 of ccid register. 4 reserved
micrel, inc. ksz8841-pmql october 2007 23 m9999-100407-1.5 bit name description 3 pme_ck pme clock when this bit is a ?1?, it indicates that t he function relies on the presence of the pci clock for pme# operation. when this bit is a ?0?, it indicates that no pci clock is required for the function to generate pme#. this bit is loaded to bi t 3 of pmcr register and bit 19 of ccid register. 2 - 0 pci: pme_ver pci: power management pci version. these bits are loaded to bits [2-0] of the pmcr register and bits [18-16 ] of the ccid register. table 3. ksz8841-pmql configparam in eeprom format loopback support the ksz8841-pmql provides loopback support for remote diag nostic failure. in loopback mode, the speed at the phy port will be set to 100base-tx full-dupl ex mode. the ksz8841-pmql only suppor ts near-end (r emote) loopback. near-end (remote) loopback is conducted at phy port 1 of the ksz8841-pmql. the loopba ck path starts at the phy ports receive inputs (rxpx/rxmx), wr aps around at the same phy port?s pmd/pma, and ends at the phy ports transmit outputs (txpx/txmx). bit [1] of register p1phyctrl is used to enable near-end lo opback for port 1. alternatively, bit [9] of register p1scslmd can also be used to enable near-end loopback. the port ?s near-end loopback path is illustrated in the following figure 4. pci bus i/f unit rx/tx dma 8k rx/tx buffer mac1 pcs1 pmd1/pma1 rxp1 / rxm1 txp1 / txm1 phy port 1 near-end (remote) loopback figure 6. port 1 near-end (remote) loopback path
micrel, inc. ksz8841-pmql october 2007 24 m9999-100407-1.5 host communication the descriptor lists and data buffers, collectively called the host communication, manage the actions and status related to buffer management. commands and signals that control the functional operation of the ksz8841-pmql are also described. the ksz8841-pmql and the driver communicate through the two data structures: command and status registers (csrs) and descriptor lists and data buffers. note: all unused bits of the data structure in this section are reserved and should be written by the driver as zeros. host communication descriptor lists and data buffers the ksz8841-pmql transfers received data frames to the re ceive buffer in host memory and transmits data from the transmit buffers in host memory. descriptors that reside in the host memory act as pointers to these buffers. there are two descriptor list s (one for receive and one for transmit) for t he mac dma. the base address of each list is written in the tdlb register and in the rdlb register, respectively. a descriptor li st is forward linked. the last descriptor may point back to the first entry to create a ring structure. descriptors are chained by setting the next address to the next buffer in both receive and transmit descriptors. the descriptor lists reside in the host physical memory address space. each pointer points to one buffer and the second pointer points to the next descriptor. this enables t he greatest flexibility for the host to chain any data buffers with discontinuous memory location. this eliminates processo r-intensive tasks such as me mory copying from the host to memory. a data buffer contains either an entire frame or part of a fr ame, but it cannot exceed a singl e frame. buffers contain only data; and buffer status is maintained in the descriptor. data chaining refers to frames that span multiple data buffers. data chaining can be enabled or disabled. data buffers reside in host physical memory space. receive descriptors (rdes0-rdes3) receive descriptor and buffer addresses must be word align ed. each receive descriptor provides one frame buffer, one byte count field, and control and status bits. the following table shows the rdes0 register bit fields. bit description 31 own own bit when set, indicates that the descript or is owned by the ksz8841-pmql. when reset, indicates that the descriptor is owned by the host. the ksz8841-pmql clears this bit either when it completes the frame rec eption or when the buffers that are associated with this descriptor are full. 30 fs first descriptor when set, indicates that this descriptor contains the first buffer of a frame. if the buffer size of the first buffer is 0, t he next buffer contains the beginning of the frame. 29 ls last descriptor when set, indicates that the buffer pointed by this descriptor is the last buffer of the frame. 28 ipe ip checksum error when set, indicates that the received frame is an ip packet and its ip checksum field does not match. this bit is valid only when last descriptor is set. 27 tcpe tcp checksum error when set, indicates that the received frame is a tcp/ip packet and its tcp checksum field does not match. this bit is valid only when last descriptor is set.
micrel, inc. ksz8841-pmql october 2007 25 m9999-100407-1.5 bit description 26 udpe udp checksum error when set, indicates that the received frame is an udp/ip packet and its udp checksum field does not match. this bit is valid only when last descriptor is set. 25 es error summary indicates the logical or of the following rdes0 bits: crc error frame too long runt frame this bit is valid only when last descriptor is set. 24 mf multicast frame when set, indicates that this frame has a multicast address. this bit is valid only when last descriptor is set. 23 - 20 spn switch engine source port number this field indicates the source port where the packet originated. if bit 20 is set, it indicates the packet was received from port 1. if bit 21 is set, it indicates the packet was received from port 2. this field is valid only when the last descriptor is set. (bits 23 and 22 are not used, but reserved for bac kward compatibility and future expansion.) 19 re report on mii error when set, indicates that a receive error in the physical layer was reported during the frame reception. 18 tl frame too long when set, indicates that the frame length exceeds the maximum size of 1518 bytes. this bit is valid only when last descriptor is set. note: frame too long is only a frame length indication and does not cause any frame truncation. 17 rf runt frame when set, indicates that this frame was damage d by a collision or premature termination before the collision window has passed. runt fr ames are passed on to the host only if the pass bad frame bit is set. 16 ce crc error when set, indicates that a crc error occurred on the received frame. this bit is valid only when last descriptor is set. 15 ft frame type when set, indicates that the frame is an ether net-type frame (frame length field is greater than 1500 bytes). when clear, indicates t hat the frame is an ieee 802.3 frame. this bit is not valid for runt frames. this bit is valid only when last descriptor is set. 14 - 11 reserved 10 - 0 fl frame length indicates the length, in bytes, of the received frame, including the crc. this field is valid only when last descriptor is set and descriptor error is reset.
micrel, inc. ksz8841-pmql october 2007 26 m9999-100407-1.5 the following table shows the rdes1 register bit fields. bit description 31 - 26 reserved 25 rer receive end of ring when set, indicates that the descriptor list reached its final descriptor. the ksz8841-pmql returns to the base address of the list, thus creating a descriptor ring. 24 - 12 reserved 10 - 0 rbs receive buffer size indicates the size, in bytes, of the receive data buffer. if the field is 0, the ksz8841-pmql ignores this buffer and moves to the next descriptor. the buffer size must be a multiple of 4. the following table shows the rdes2 register bit fields. bit description 31 - 0 buffer address indicates the physical memory address of the buffer. the buffer address must be word aligned. the following table shows the rdes3 register bit fields. bit description 31 - 0 next descriptor address indicates the physical memory address of th e next descriptor in the descriptor ring. the buffer address must be word aligned. transmit descriptors (tdes0-tdes3) transmit descriptors must be word aligned. each descrip tor provides one frame buffer, one byte count field, and control and status bits. the following table shows the tdes0 register bit fields. bit description 31 own own bit when set, indicates that the descriptor is owned by the ksz8841-pmql. when cleared, indicates that the descriptor is owned by the host. the ksz8841-pmql clears this bit either when it completes the frame transmission or when the buffer allocated in the descriptor is empty. the ownership bit of the first descriptor of the frame should be set after all subsequent descriptors belonging to the same frame have been set. this avoids a possible race condition between the ksz8841-pmql fetching a descriptor and the driver setting an ownership bit. 30 - 0 reserved the following table shows the tdes1 register bit fields. bit description 31 ic interrupt on completion when set, the ksz8841-pmql sets transmit inte rrupt after the present frame has been transmitted. it is valid only when last segment is set. 30 fs first segment when set, indicates that the buffer cont ains the first segment of a frame.
micrel, inc. ksz8841-pmql october 2007 27 m9999-100407-1.5 bit description 29 ls last segment when set, indicates that the buffer cont ains the last segment of a frame. 28 ipckg ip checksum generate when set, the ksz8841-pmql will generate correct ip checksum for outgoing frames that contains ip protocol header. the ksz8841-pm ql supports only a standard ip header, i.e., ip with a 20 byte header. when this feat ure is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the ip checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 27 tcpckg tcp checksum generate when set, the ksz8841-pmql will generate correct tcp checksum for outgoing frames that contains ip and tcp protocol header. the ksz8841-pmql supports only a standard ip header, i.e., ip with a 20 byte header. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the tcp checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 26 udpckg udp checksum generate when set, the ksz8841-pmql will generate correct udp checksum for outgoing frames that contains an ip and udp protocol header. t he ksz8841-pmql supports only a standard ip header, i.e., ip with a 20 byte header. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the udp checksum generate bit in the transmit mode register is not set. 25 ter transmit end of ring when set, indicates that the descriptor po inter has reached its final descriptor. the ksz8841-pmql returns to the base address of the list, forming a descriptor ring. 24 reserved 23 ? 20 spn switch engine destination port map when set, this field indicates the destinatio n port(s) where the packet will be forwarded to. if bit 20 is set, it indicates the packet was received from port 1. if bit 21 is set, it indicates the packet was received from port 2. setting all ports to 1 will cause the controller engine to broadcast the packet. setting all bits to 0 has no effect. the controll er engine forwards the packet according to its internal controller lookup algorithm. this field is valid only when the last descriptor is set. (bits 23 and 22 are not used, but reserved for backward compatibility and future expansion.) 19 - 11 reserved 10 - 0 tbs transmit buffer size indicates the size, in bytes, of the transmit data buffer. if this field is 0, the ksz8841-pmql ignores this buffer and moves to the next descriptor.
micrel, inc. ksz8841-pmql october 2007 28 m9999-100407-1.5 the following table shows the tdes2 register bit fields. bit description 31 - 0 buffer address indicates the physical memory address of the buffer. there is no limitation on the transmit buffer address alignment. the following table shows the tdes3 register bit fields. bit description 31 - 0 next descriptor address indicates the physical memory address of th e next descriptor in the descriptor ring. the buffer address must be word aligned. pci configuration registers the ksz8841-pmql implements 12 configurat ion registers. these regi sters are described in the following subsections. the ksz8841-pmql enables a full software- driven initialization and configuration. this allows the software to identify and query the ksz8841-pmql. the ksz8841-pmql treats configur ation space write operations to registers that are reserved as no-ops. that is, the access completes normally on the bus and the data is discarded. read accesses, to reserved or unimplemented registers, complete normally and a data value of 0 is returned. software reset has no effect on the confi guration registers. hardware reset sets the configuration registers to their default values. configuration register identifier i/o address offset default identification cfid 0x00 0x884116c6 command and status cfcs 0x04 0x02*00000 revision cfrv 0x08 0x02000010 latency timer cflt 0x0c 0x00000000 base memory address cbma 0x10 0x00000000 reserved ? 0x14-28 0x00000000 subsystem id csid 0x2c 0x******** capabilities pointer ccap 0x34 0x******** reserved ? 0x38 0x00000000 interrupt cfit 0x3c 0x28140100 reserved ? 0x40-4c 0x00000000 capability id ccid 0x50 0x***20001 power management control and status cpmc 0x54 0x00000000
micrel, inc. ksz8841-pmql october 2007 29 m9999-100407-1.5 configuration id register (cfid offset 00h) the cfid register identifies the ksz8841-pmql. the fo llowing table shows the cfid register bit fields. bit default description 31 - 16 0x8841 device id 15 - 0 0x16c6 vendor id specifies the manufacturer of the ksz8841-pmql. the following table shows the ac cess rules of the register. command and status configuration register (cfcs offset 04h) the cfcs register is divided into two sections: a command register (cfcs[15:0]) and a stat us register (cfcs[31:16]). the command register provides control of the ksz8841-pmql?s ability to generate and re spond to pci cycles. when 0 is written to this register, the ksz8841-pmql logically disconnects from the pci bus for all accesses except configuration accesses. the status register records status information for the pci bus-related ev ents. the cfcs status bits are not cleared when they are read. writing 1 to these bi ts clears them; writing 0 has no effect. the following table describes the cfcs register bit fields. bit type default description 31 status 0 detected parity error when set, indicates that the ksz8841-pmql detected a parity error, even if parity error handling is disabled in parity error response (cfcs[6]). 30 status 0 signal system error when set, indicates that the ksz 8841-pmql asserted the system error serr_n pin. 29 status 0 received master abort when set, indicates that the ksz8841-pmql terminated a master transaction with master abort. 28 status 0 received target abort when set, indicates that the ksz8841-pmql master transaction was terminated due to a target abort. 27 status 0 target abort this bit is set by ksz8841-pmql whenever it terminates with a target abort. the csr registers are all 32-bit little endian format. for pci register read cycles, the ksz8841-pmql allows any different combination of cben. for pci register bus cycles, only byte, word (16-bit), or dword (32-bit) accesses are allowed. any other combination is illegal and is target aborted. 26 - 25 status 01 device select timing indicates the timing of the asse rtion of device select(devsel_n). these bits are fixed at 01, whic h indicates a medium assertion of devsel_n. category description value after hardware reset 0x884116c6 write access rules write has no effect on the ksz8841-pmql.
micrel, inc. ksz8841-pmql october 2007 30 m9999-100407-1.5 bit type default description 24 status 0 data parity report this bit is set when the following conditions are met: the ksz8841-pmql asserts parity error perr_n or it senses the assertion of perr_n by another device. the ksz8841-pmql operates as a bus master for the operation that caused the error. parity error response (cfcs[6]) is set. 23 - 22 reserved 00 reserved 21 status 0 66mhz capable 0 = not 66mhz capable 20 status - new capability indicates whether or not the ksz8841-pmql implements a list of new capabilities. when set, this bit indicates the presence of new capabilities. when reset, new capabilities are not implemented. the value of this bit is loaded from the new_cap bit in eeprom. 19 - 9 reserved 0x000 reserved 8 command 0 system error enable when set, the ksz8841-pmql asserts system error (serr_n) when it detects a parity error on the address phase. 7 reserved 0 reserved 6 command 0 parity error response when set, the ksz8841-pmql asserts fatal bus error after it detects a parity error. when reset, any detected parity error is ignored and the ksz8841-pmql continues normal operation. parity checking is disabled after hardware reset. 5 - 3 reserved 000 reserved 2 command 0 master operation when set, the ksz8841-pmql is capable of acting as a bus master. when reset, the ksz8841-pmql capability to generate pci accesses is disabled. for normal operation, this bit must be set. 1 command 0 memory space access when set, the ksz8841-pmql responds to memory space accesses. when reset, the ksz8841-pmql does not respond to memory space accesses. 0 reserved 0 reserved
micrel, inc. ksz8841-pmql october 2007 31 m9999-100407-1.5 configuration revision register (cfrv offset 08h) the cfrv register contains the ksz8841-pmql revision num ber. the following table s hows the cfrv register bit fields. bit default description 31 - 24 0x02 base class indicates the network controller, and is equal to 0x2. 23 - 16 0x00 subclass indicates the fast/gigabit ethernet chip, and is equal to 0x00. 15 - 8 0x00 reserved 7 - 4 0x1 revision number indicates the ksz8841-pmql revision num ber, and is equal to 0x1. this number is incremented for subsequent revision. 3 - 0 0x0 step number indicates the ksz8841-pmql step number, and is equal to 0x0 (chip revision a). this number is incremented for subsequent ksz8841-pmql steps within the current revision. configuration latency timer register (cflt offset 0ch) this register configures the cache line size field and the latency timer. the following table shows the cflt register bit fields. bit default description 31 - 16 0x00 reserved 15 - 8 0x00 configuration latency timer specifies, in units of pci bus clocks, the value of the latency timer of the ksz8841-pmql. when the ksz8841-pmql asserts frame_n, it enables its latency timer to count. if the ksz8841-pmql deserts frame_n prior to count expiration, the content of t he latency timer is ignored. otherwise, after the count expires, the ks z8841-pmql initiates transaction termination as soon as its gnt_n is deserted. 7 - 0 0x00 cache line size specifies, in unit of 32-bit words( dword), the system cache line size. configuration base memory address register (cbma offset 10h) the cbma register specifies the base memory address for accessing the ksz884 1-pmql csrs. this register must be initialized prior to accessing any csr with memory access. the following table shows the cbma register bit fields. bit default description 31 - 11 0 configuration base memory address defines the base address assigned for mapping the ksz8841-pmql csrs. 10 - 1 0 this field value is 0 when read. 0 0 memory space indicator determines that the register maps into the memory space. the value in this field is 0. this is a read-only field.
micrel, inc. ksz8841-pmql october 2007 32 m9999-100407-1.5 subsystem id register (csid offset 2ch) the csid register is a read- only 32-bit register. the co ntent of the csid is loaded from the eeprom after hardware reset. the loading period lasts at least 27,400 pci cycles when the system is in 33mhz mode, and starts 50 cycles after hardware reset dese rtion. if the host accesses the csid before its content is loaded from the eeprom, the ksz8841-pmql responds with retry termination on the pci bus. the following table shows the csid register bit fields. bit description 31 - 16 subsystem id indicates a 16-bit field containing the subsystem id. 15 - 0 subsystem vendor id indicates a 16-bit field containing the subsystem vendor id. the following table shows the ac cess rules of the register. capabilities pointer register (ccap offset 34h) the ccap register points to the base addr ess of the power management register block in the configuration address space. this pointer is valid only if the new capability bit in cfcs is set. the following table shows the ccap register bit fields. bit default description 31 - 8 0x000000 reserved 7 - 0 -- capabilities pointer points to the location of the power ma nagement register block in the pci configuration space. the value of this field is determined by the new capabilities bit 15 in the eeprom. if this bit is set, the value of this field is 0x50, which stands for support power management. otherwise, this field is read as 0x00. configuration interrupt register (cfit offset 3ch) the cfit register is divided into two sections: the interrupt line and the interrupt pin. cfit configures both the system?s interrupt and the ksz8841-pmql interrupt pin connection. the following table shows the cfit register bit fields. bit default description 31 - 24 0x28 max_lat this field indicates how often the device needs to gain access to the pci bus. time unit is equal to 0.25 us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 0x28 (10 us). 23 - 16 0x14 min_gnt this field indicates the burst period le ngth that the device needs. time unit is equal to 0.25us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 0x14 (5 us). 15 - 8 0x01 interrupt pin indicates which interrupt pin that the ksz8841-pmql uses. the ksz8841- pmql uses inta# and the read value is 0x01. 7 - 0 0x00 interrupt line category description value after hardware reset read from eeprom. write access rules write has no effect on the ksz8841-pmql.
micrel, inc. ksz8841-pmql october 2007 33 m9999-100407-1.5 bit default description provides interrupt line routing infor mation. the basic input/output system (bios) writes the routing information into to this field when it initialized and configures the system. the value in th is field indicates wh ich input of the system interrupt controller is connec ted to the k8841p?s interrupt pin. the driver can use this information to det ermine priority and vector information. values in this field are system architecture specific. the following table shows the ac cess rules of the register. category description value after hardware reset 0x281401xx capabilities id register (ccid offset 50h) the ccid register is a read-only register that pr ovides information on the ksz8841-pmql power management capabilities. the following table shows the ccid register bit fields. the ccid register bi ts [31-16] are mirrored with pmcr register bits [15-0]. bit default description 31 0 pme support d3 (cold) if this bit is set, the ksz8841-pmql asserts pme in d3(cold) power state. otherwise, the ksz8841-pmql does not assert pme in d3(cold). the value of this bit is loaded from the pme_d3_cold bit in the eeprom. 30 1 pme support d3 (hot) the value of this bit is 1, indica ting that the ksz8841-pmql may assert pme in d3(hot) power state. 29 0 pme support d2 if this bit is set, the ksz8841-pmql asserts pme in d2 power state. otherwise, the ksz8841-pmql does not assert pme in d2 state. the value of this bit is loaded fr om the pme_d2 bit in the eeprom. 28 0 pme support d1 if this bit is set, the ksz8841-pmql asserts pme in d1 power state. otherwise, the ksz8841-pmql does not assert pme in d1 state. the value of this bit loaded from the pme_d1 bit in the eeprom. 27 0 pme support d0 1 the value of this bit is 0, indica ting that the ksz8841-pmql does not assert pme in d0 power state. 26 0 d2 support if this bit is set, it indicates that the ksz8841-pmql support d2 power state. the value of this bit is loaded fr om the d2_sup bit in the eeprom. 1 references to d0, d1, d2, and d3 are power management states defined in a similar fashion to the way they are defined for pci. for more information, refer to the pci specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.
micrel, inc. ksz8841-pmql october 2007 34 m9999-100407-1.5 bit default description 25 0 d1 support if this bit is set, it indicates that the ksz8841-pmql support d1 power state. the value of this bit loaded from the d1_sup bit in the eeprom. 24 - 22 000 auxiliary current this 3-bit field reports the 3.3vaux au xiliary current requirements for the pci function. if pme# generation from d3_cold is not supported by the function, this field must return a value of 000 when read. 21 0 device specific initialization indicates whether special initialization of this function is required (beyond the standard pci configuration header) before the generic class device driver is able to use it. note that this bit is not used by some operating systems. microsoft windows and windows nt, for instance, do not use this bit to determine whether to use d3. instead, they use the driver?s capabilities to determine this. a ?1? indicates that the function requ ires a device specific initialization sequence following transition to the d0 uninitialization state. the value of this bit is loaded from the pme_dsi bit in the eeprom. 20 0 reserved should be set to 0. 19 0 pme clock when this bit is a ?1?, it indicates that the function relies on the presence of the pci clock for pme# operation. when this bit is a ?0?, it indicates that no pci clock is required for the function to generate pme#. the value of this bit is loaded from the pme_ck bit in the eeprom. 18 - 16 0 power management pci version the value of this bit is loaded from the pme_ver[2:0] bits in the eeprom. 15 - 8 0x00 next item pointer points to the location of the next bl ock of the capabilities list in the pci configuration space. the va lue of this field is 0x00 , indicating that this is the last item of the capability linked list. 7 - 0 0x01 capabilities id pci power management registers id. the value of this field is 01h, indicating that this is the po wer-management register block. the following table shows the ac cess rules of the register. category description value after hardware re set 0x40000001 & eeprom write access rules write has no effect on the ksz8841-pmql
micrel, inc. ksz8841-pmql october 2007 35 m9999-100407-1.5 power-management control and stat us register (cpmc offset 54h) the cmpc register is a power-managem ent control and status register. this register can control and sate power management events. the following table shows the cmpc register bit fields. bit default description 31 - 16 0x0000 reserved 15 0 pme_status this bit indicates that the ksz8841-pmql has detected a power- management event. if bit pme_enable is set, the ksz8841-pmql also asserts the pme_n pin. this bit is cleared on power-up reset or by write 1. it is not modified by either hardware or software reset. when this bit is cleared, the ksz8841-pmql deserts the pme_n pin. 14 - 9 0x00 reserved 8 0 pme_enable if this bit is set, the ksz8841-pmql can assert the pme_n pin. otherwise, assertion of the pme_n pin is disabled. this bit is cleared on power-up reset only and is not modified by either hardware or software reset. 7 - 4 0x0 reserved 3 0 no soft reset if this bit is set (?1?), the ksz8841-pmql does not perform an internal reset when transitioning from d3_hot to d0 because of powerstate commands. configuration context is pr eserved. upon transition from d3_hot to the d0 initialized stat e, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. if this bit is cleared (?0?), the ksz8841-pmql does perform an internal reset when transitioning from d3_hot to d0 via software control of the powerstate bits. configuration context is lost when performing the soft reset. upon transition from d3_hot to the d0 state, f ull reinitialization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transition from d3_hot to d0 by a system or bus segment reset will return to the device state d0 uninitialized with only pme context preserved if pme is supported and enabled. 2 0 reserved 1 - 0 00 power state this field is used to set the curr ent power state of the ksz8841-pmql and to determine its power state. the definitions of the field values are: 0: d0 1: d1 2: d2 3: d3(hot) this field gets a value of 0 after power up.
micrel, inc. ksz8841-pmql october 2007 36 m9999-100407-1.5 the following table shows the ac cess rules of the register. category description bit 15 read/write 1 clear (rw1c) bit 8 read/write (rw) bit 3 read only (ro) bit 1 ? 0 read write (rw) pci control & status registers the pci csr registers are all 32 bit in little endian form at. for pci register read cycle, the ksz8841-pmql allows any different combination of cben. for pci register bus cycl es, only byte, word(16-bit), or dword(32-bit) accesses are allowed. any other combinations ar e illegal, and will be target aborted. all other registers not included below are reserved. mac dma transmit control register (mdtxc offset 0x0000) the mac dma transmit control register establishes the transmit operating modes and commands for the port. this register should be one of the last csrs to be wr itten as part of the transmit initialization. the following table shows the register bit fields. bit default read/ write description 31-30 - ro reserved 29 - 24 0x00 rw mtbs dma transmit burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the mac dma burst size is limited only by the amount of data stored in the transmit buffer before issuing a bus request. the mtbs can be programmed with permissib le values 0,1, 2, 4, 8, 16, or 32. after reset, the mtbs default is 0, i.e. unlimited. 23 - 19 0x00 ro reserved 18 0 rw mtucg mac transmit udp checksum generate when set, the ksz8841-pmql will generate correct udp checksum for outgoing udp/ip frames at port. when this bit is set, add crc should also turn on. 17 0 rw mttcg mac transmit tcp checksum generate when set, the ksz8841-pmql will generate correct tcp checksum for outgoing tcp/ip frames at port. when this bit is set, add crc should also turn on. 16 0 rw mticg mac transmit ip checksum generate when set, the ksz8841-pmql will generate correct ip checksum for outgoing ip frames at port. when this bit is set, add crc should also turn on. 15 - 10 0x00 ro reserved 9 0 rw mtfce mac transmit flow control enable when this bit is set and the ksz8841-pmql is in full duplex mode, flow control is enabled and the ksz8841-pmql will transmit a pause frame when the receive buffer capacity has reached a level that may cause the buffer to overflow. when this bit is set and the ksz8841-pmql is in half duplex mode, back-
micrel, inc. ksz8841-pmql october 2007 37 m9999-100407-1.5 bit default read/ write description pressure flow control is enabled. when this bit is cleared, no transmit flow control is enabled. 8 - 3 0x0 ro reserved 2 0 rw mtep mac dma transmit enable padding when set, the ksz8841-pmql automatically adds a padding field to a packet shorter than 64 bytes. note: setting this bit automatically enables add crc feature. 1 0 rw mtac mac dma transmit add crc when set, the ksz8841-pmql appends the crc to the end of the transmission frame. 0 0 rw mte mac dma tx enable when the bit is set, the mdma tx block is enabled and placed in a running state. when reset, the transmission pr ocess is placed in the stopped state after completing the transmission of the current frame. the stop transmission command is effective only when the transmission process is in the running state. mac dma receive control register (mdrxc offset 0x0004) the mac dma receive control register establishes t he receive operating modes and commands for the port. this register should be one of the last csrs to be written as part of the receive initialization. the following table shows the register bit fields. bit default read/ write description 31 - 30 00 ro reserved 29 - 24 0x00 rw mrbs dma receive burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the mac dma burst size is limited only by the amount of data stored in the receive buffer before issuing a bus request. the mrbs can be programmed with permissib le values 0,1, 2, 4, 8, 16, or 32. after reset, the mrbs default is 0, i.e. unlimited. 23 - 20 0x0 ro reserved 19 0 rw ip header alignment enable 1 = enable alignment of ip header to dword address. layer 2 header will not be dword aligned anymore. please l ook at rx descriptor 0 for the layer 2 header address shift. 0 = ip header alignment disabled. 18 0 rw mrucc mac receive udp checksum check when set, the ksz8841-pmql will check for correct udp checksum for incoming udp/ip frames at port. packets received with incorrect udp checksum will be discarded. 17 0 rw mrtcg mac receive tcp checksum check when set, the ksz8841-pmql will check for correct tcp checksum for incoming tcp/ip frames at port. packets received with incorrect tcp checksum will be discarded. 16 0 rw mricg mac receive ip checksum check when set, the ksz8841-pmql will check for correct ip checksum for
micrel, inc. ksz8841-pmql october 2007 38 m9999-100407-1.5 bit default read/ write description incoming ip frames at port. packets received with incorrect ip checksum will be discarded. 15 - 10 0x00 ro reserved 9 0 rw mrfce mac receive flow control enable when this bit is set and the ksz8841-pmql is in full duplex mode, flow control is enabled and the ksz8841-pmql will acknowledge a pause frame from mac of the controller, t he outgoing packets will be pending in the transmit buffer until the pause control timer expires. this field has no meaning in half-duplex mode and should be programmed to 0. when this bit is cleared, no flow control is enabled. 8 - 7 00 ro reserved 6 0 rw mrb mac receive broadcast when set, the mac receive all broadcast frames. 5 0 rw mrm mac receive multicast when set, the mac receive all multicast frames (including broadcast). 4 0 rw mru mac receive unicast when set, the mac receive unicast fram es that match the 48-bit station address of the mac. 3 0 rw mre mac dma receive error frame when set, the ksz8841-pmql will pass the errors frames received to the host. error frames include runt frames, oversized frames, crc errors. 2 0 rw mra mac dma receive all when set, the ksz8841-pmql receives all incoming frames, regardless of its destination address. 1 0 rw dma receive multicast hash-table enable setting this bit enables the rx function to receive multicast frames that pass the crc hash filtering mechanism. 0 0 rw mre mac dma rx enable when the bit is set, the dma rx block is enabled and placed in a running state. when reset, the receive process is placed in the stopped state after completing the reception of the cu rrent frame. the stop transmission command is effective only when the re ception process is in the running state. mac dma transmit start command register (mdtsc offset 0x0008) this register is written by the cpu when packets in the data buffer need to be transmitted. the following table shows the register bit fields. bit default read/ write description 31 - 0 0x00000000 wo wtsc transmit start command when written with any value, the transmit dma checks for frames to be transmitted. if no descriptor is available, the transmit process returns to suspended state. if descriptiors ar e available, the transmit process starts or resumes. this bit is self-clearing.
micrel, inc. ksz8841-pmql october 2007 39 m9999-100407-1.5 mac dma receive start command register (mdrsc offset 0x000c) this register is written by t he cpu when there are frame data in receive buffer to be processed. the following table shows the register bit fields. bit default \ read/ write description 31 - 0 0x00000000 wo wrsc receive start command when written with any value, the receive dma checks for descriptors to be acquired. if no descriptor is available, the receive process returns to suspended state and wait for t he next receive restart command. if descriptors are available, the receive process resumes. this bit is self- clearing. transmit descriptor list base address register (tdlb offset 0x0010) this register is used for transmit descript or list base address register. the register is used to point to the start of the appropriate descriptor list. writing to this register is permi tted only when its respective pr ocess is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8841-pmql behavior is unpredictable when the lists are not wor d- aligned. the following table shows the register bit fields. bit default read/ write description 31 - 0 0x00000000 rw wstl start of transmit list note: write can only occur when t he transmit process stopped. receive descriptor list base address register (rdlb offset 0x0014) this register is used for receive descriptor list base address re gister. the register is used to point to the start of the appropriate descriptor list. writing to this register is permi tted only when its respective pr ocess is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8841-pmql behavior is unpredictable when the lists are not wor d- aligned. the following table shows the register bit fields. bit default read/ write description 31 - 0 0x00000000 rw wsrl start of receive list note: write can only occur when t he transmit process stopped. mac multicast table 0 register (mtr0 offset 0x0020) the 64 bit multicast table is used for group address filtering. the value is defined as the six most significant bits of the crc of the da. the two most significant bi ts select the register to be used, while the other determines the bit within the register. bit default read/ write description 31-0 0x00000000 rw mtr0 multicast table 0 when appropriate bit is set, the packet received with da matches the crc hashing function is received without being filtered. note: when receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr then all multicast addresse s are received regardless of the multicast table value.
micrel, inc. ksz8841-pmql october 2007 40 m9999-100407-1.5 mac multicast table 1 register (mtr1 offset 0x0024) the 64 bit multicast table is used for group address filtering. the value is defined as the six most significant bits of the crc of the da. the two most significant bi ts select the register to be used, while the other determines the bit within the register. bit default read/ write description 31-0 0x00000000 rw mtr0 multicast table 1 when appropriate bit is set, the packet received with da matches the crc hashing function is received without being filtered. note: when receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr then all multicast addresses are received regardless of the multicast table value. interrupt enable register (inten offset 0x0028) this register enables the in terrupts from the internal or external sources. the following table shows the register bit fields. bit default read/ write description 31 0 rw dmlcie dma mac link changed interrupt enable when this bit is set, the dma mac link changed interrupt is enabled. when this bit is reset, the dma mac link changed interrupt is disabled. 30 0 rw dmtie dma mac transmit interrupt enable when this bit is set, the dma mac transmit interrupt is enabled. when this bit is reset, the dma mac transmit interrupt is disabled. 29 0 rw dmrie dma mac receive interrupt enable when this bit is set, the dma mac receive interrupt is enabled. when this bit is reset, the dma mac receive interrupt is disabled. 28 0 rw dmtbuie dma mac transmit buff er unavailable interrupt enable when this bit is set, the dma mac transmit buffer unavailable interrupt is enabled. when this bit is reset, the dma mac transmit buffer unavailable interrupt is disabled. 27 0 rw dmrbuie dma mac receive buffer un available interrupt enable when this bit is set, the dma mac receive buffer unavailable interrupt is enabled. when this bit is reset, the dma mac receive buffer unavailable interrupt is disabled. 26 0 rw dmtpsie dma mac transmit pr ocess stopped interrupt enable when this bit is set, the dma mac transmit process stopped interrupt is enabled. when this bit is reset, the dma mac transmit process stopped interrupt is disabled.
micrel, inc. ksz8841-pmql october 2007 41 m9999-100407-1.5 bit default read/ write description 25 0 rw dmrpsie dma mac receive pro cess stopped interrupt enable when this bit is set, the dma mac receive process stopped interrupt is enabled. when this bit is reset, the dma mac receive process stopped interrupt is disabled. 24 - 0 - ro reserved interrupt status register (intst offset 0x002c) this register contains all the status bits for the arm cpu. when corresponding e nable bit is set, it cause the cpu to be interrupted. this register is us ually read by the driver during interrupt servic e routine or polling. the register bits are not cleared when read. each field can be masked. the following table shows the register bit fields. bit default read/ write description 31 0 rw dmlcs dma mac link changed status when this bit is set, it indicates that the dma mac link status has changed from link up to link down or from link down to link up. this edge-triggered interrupt status is cleared by writing 1 to this bit. 30 0 rw dmts dma mac transmit status when this bit is set, it indicates t hat the dma mac has transmitted at least a frame on the dma port and t he mac is ready for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 29 0 rw dmrs dma mac receive status when this bit is set, it indicates that the dma mac has received a frame from the dma port and it is ready for the host to process this edge-triggered interrupt status is cleared by writing 1 to this bit. 28 0 rw dmtbus dma mac transmit buffer unavailable status when this bit is set, it indicates t hat the next descriptor on the transmit list is owned by the host and cannot be acquired by the ksz8841- pmql. the transmission process is suspended. to resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit start command. this edge-triggered interrupt status is cleared by writing 1 to this bit. 27 0 rw dmrbus dma mac receive buffer unavailable status when this bit is set, it indicates that the descriptor list is owned by the host and cannot be acquired by the ksz8841-pmql. the receiving process is suspended. to resume pr ocessing receive descriptors, the host should change the ownership of the descriptor and may issue a receive start command. if no receiv e start command is issued, the receiving process resumes when the next recognized incoming frame is received. after the first assertion, this bit is not asserted for any subsequent not owned receive descriptors fetches. this bit is asserted only when the previous receive descriptor was owned by the ksz8841- pmql. this edge-triggered interrupt status is cleared by writing 1 to this bit. 26 0 rw dmtpss dma mac transmit process stopped status
micrel, inc. ksz8841-pmql october 2007 42 m9999-100407-1.5 bit default read/ write description asserted when the dma mac trans mit process enters the stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 25 0 rw dmrpss dma mac receive process stopped status asserted when the dma mac rece ive process enters the stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 24 - 0 - ro reserved mac additional station addr ess low register (maal0-15) the ksz8841-pmqlsupports 16 additional mac addresses for ma c address filtering. this mac address is used to define one of the 16 destination addresses that the ksz8841-pmql will respond to when receiving frames on the port. network addresses are generally express ed in the form of 01:23:45 :67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default read/ write description 31 - 0 -- rw maal0 mac additional st ation address 0 low 4 bytes the least significant word of the additional mac 0 station address. mac additional station addr ess high register (maah0-15) the ksz8841-pmql supports 16 additional mac addresses for mac address filtering. this mac address is used to define one of the 16 destination addresses that the ksz8841-pmql will respond to when receiving frames on the port. network addresses are generally express ed in the form of 01:23:45 :67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit default read/ write description 31 0 rw maa0e mac additional station address 0 enable when set, the additional mac address is enabled for received frames. when reset, the additional mac address is disabled. 30 - 16 0x0 ro reserved 15 - 0 -- rw maah0 mac additional stat ion address 0 high 2 bytes the most significant word of the additional mac 0 station address. the following table shows the register map for all 16 additional mac address registers. register identifier offset add mac low 0 maal0 0x0080 add mac high 0 maah0 0x0084 add mac low 1 maal1 0x0088 add mac high 1 maah1 0x008c add mac low 2 maal2 0x0090
micrel, inc. ksz8841-pmql october 2007 43 m9999-100407-1.5 register identifier offset add mac high 2 maah2 0x0094 add mac low 3 maal3 0x0098 add mac high 3 maah3 0x009c add mac low 4 maal4 0x00a0 add mac high 4 maah4 0x00a4 add mac low 5 maal5 0x00a8 add mac high 5 maah5 0x00ac add mac low 6 maal6 0x00b0 add mac high 6 maah6 0x00b4 add mac low 7 maal7 0x00b8 add mac high 7 maah7 0x00bc add mac low 8 maal8 0x00c0 add mac high 8 maah8 0x00c4 add mac low 9 maal9 0x00c8 add mac high 9 maah9 0x00cc add mac low 10 maal10 0x00d0 add mac high 10 maah10 0x00d4 add mac low 11 maal11 0x00d8 add mac high 11 maah11 0x00dc add mac low 12 maal12 0x00e0 add mac high 12 maah12 0x00e4 add mac low 13 maal13 0x00e8 add mac high 13 maah13 0x00ec add mac low 14 maal14 0x00f0 add mac high 14 maah14 0x00f4 add mac low 15 maal15 0x00f8 add mac high 15 maah15 0x00fc mac/phy and control registers mac address register low (0x0200): marl this register along with other 2 mac address registers are loade d starting at word location 0x10 of the eeprom upon hardware reset. the register can be modifi ed by software driver, but will not modi fy the original mac address value in the eeprom. these six bytes of mac addr ess in external eeprom are loaded to these three registers as mapping below: marl[15:0] = eeprom 0x1(mac byte 2 and 1) marm[15:0] = eeprom 0x2(mac byte 4 and 3) marh[15:0] = eeprom 0x3(mac byte 6 and 5) the mac address is used to define the individual destinat ion address the ksz8841-pmql responds to when receiving frames. network addresses are generall y expressed in the form of 01:23:45:67 :89:ab, where the by tes are received from left to right, and the bits within ea ch byte are received from right to left (lsb to msb). for example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
micrel, inc. ksz8841-pmql october 2007 44 m9999-100407-1.5 these three registers value for mac address 01:23:45: 67:89:ab will be held as below: marl[15:0] = 0x89ab marm[15:0] = 0x4567 marh[15:0] = 0x0123 the following table shows the register bi t fields for low word of mac address. bit default r/w description 15-0 - rw marl mac address low the least significant word of the mac address mac address register middle (0x0202): marm the following table shows the register bit fields for middle word of mac address. bit default r/w description 15-0 - rw marm mac address middle the middle word of the mac address mac address register high (0x0204): marh the following table shows the register bi t fields for high word of mac address. bit default r/w description 15-0 - rw marh mac address high the most significant word of the mac address on-chip bus control register (offset 0x0210): obcr this register controls the on-chip bus speed for the ks z8841-pmql operations. it?s used for power management when the external host cpu is running a slow frequency. the default of the on-chip bus speed is 25mhz. when the external host cpu is running at a higher clock rate, it?s recommended the on-chip bus is adjusted accordingly for the best performance. bit default r/w description 15-2 - ro reserved 1-0 0x3 rw obsc on-chip bus speed control 00: 125 mhz 01: 62.5 mhz 10: 41.66 mhz 11: 25 mhz eeprom control register (offset 0x0212): eepcr ksz8841-pmql supports both with and without eeprom system design. to support external eeprom, tie the eeprom enable (eeen) pin to high; otherwise, tie it to low (or no connect). also, ksz8 841-pmql allows software to access (read and write) eeprom directly. that is, t he eeprom access timing can be fu lly controlled by software if eeprom software access bit is set. bit default r/w description 15-5 0 ro reserved 4 0 rw eesa eeprom software access 1 = enable software to access eeprom through bit 14 to bit 11. 0 = disable software to access eeprom.
micrel, inc. ksz8841-pmql october 2007 45 m9999-100407-1.5 bit default r/w description 3 00 ro eecb eeprom status bits bit 3: data receive from eeprom. this bit directly reflects the value of the eedi pin. 2 00 rw eecb eeprom control bits bit 2: data in to eeprom. this bit directly controls the device?s the eedo pin. 1 00 rw eecb eeprom control bits bit 1: serial clock. this bit direct ly controls the device?s the eesk pin. 0 00 rw eecb eeprom control bits bit 0: chip select. this bit directly controls the device?s the eecs pin. memory bist info register (offset 0x0214): mbir the following table shows the register bit fields. bit default r/w description 15-13 0x0 ro reserved 12 - ro txmbf tx memory bits finish when set, it indicates the memory built in self test has completed for the tx memory. 11 - ro txmbfa tx memory bits fail when set, it indicates the memory built in self test has failed. 10-5 - ro reserved 4 - ro rxmbf rx memory bits finish when set, it indicates the memory built in self test has completed for the rx memory. 3 - ro rxmbfa rx memory bits fail when set, it indicates the memory built in self test has failed. 2-0 - ro reserved global reset register (offset 0x0216): grr this register holds control information programmed by the cpu to control the gl obal soft reset function. bit default r/w description 15-1 0x00 ro reserved 0 0 rw global soft reset 1 = software reset active 0 = software reset inactive soft reset will affect all of the registers except pci configuration registers.
micrel, inc. ksz8841-pmql october 2007 46 m9999-100407-1.5 power management capabilities register (offset 0x0218): pmcr this register is a read-only register that provides information on the ksz 8841-pmql power manage ment capabilities. these bits are automatically downloaded from the configparam word of eeprom , if pin eeen is pulled high (enable eeprom). the pmcr register bits [15-0] ar e mirrored to ccid register bits [31-16]. bit default r/w description 15 0 ro pme support d3 (cold) this bit is 0 only; the ksz884 1-pmql does not support pme in d3(cold) power state. 14 1 ro pme support d3 (hot) this bit is 1 only, it is indicatin g that the ksz8841-pmql can assert pme event (pmen pin 14) in d3(hot) power state. 13 0 ro pme support d2 if this bit is set, the ksz8841-pmql asserts pme event (pmen pin 14) when the ksz8841pmql is in d2 power state and pme_en (see bit8 in pmcs register) is set. otherwise, the ksz8841pmql does not assert pme event (pmen pin 14) when the ksz8841pmql is in d2 power state. the value of this bit is loaded from the pme_d2 bit in the eeprom 0x6 word. 12 0 ro pme support d1 if this bit is set, the ksz8841-pmql asserts pme event (pmen pin 14) when the ksz8841-pmql is in d1 power state and pme_en (see bit8 in pmcs register) is set. otherwise, the ksz8841m does not assert pme event (pmen pin 14) when the ksz8841m is in d1 power state. the value of this bit loaded from the pme_d1 bit in the eeprom 0x6 word. 11 0 ro pme support d0 this bit is 0 only, it indicates t hat the ksz8841-pmql does not assert pme event (pmen pin 14) in d0 power state. 10 0 ro d2 support if this bit is set, it indicates that the ksz8841-pmql support d2 power state. the value of this bit is loaded from the d2_sup bit in the eeprom 0x6 word. (this bit is 0 only if without eeprom). 9 0 ro d1 support if this bit is set, it indicates that the ksz8841-pmql support d1 power state. the value of this bit loaded from the d1_sup bit in the eeprom 0x6 word. (this bit is 0 only if without eeprom). 8 - 6 000 ro auxiliary current this 3-bit field reports the 3.3vaux auxiliary current requirements for the pci function. if pme# generation from d3_cold is not supported by the function, this field must return a value of 000 when read. 5 0 ro device specific initialization indicates whether special initializa tion of this function is required (beyond the standard pci confi guration header) before the generic class device driver is able to use it. note that this bit is not used by some operating systems. microsoft windows and windows nt, for instance, do not use this bit to determine whether to use d3. instead, they use the driver?s capabilities to determine this.
micrel, inc. ksz8841-pmql october 2007 47 m9999-100407-1.5 bit default r/w description a ?1? indicates that the function requ ires a device specific initialization sequence following transition to the d0 uninitialization state. the value of this bit is loaded fr om the pme_dsi bit in the eeprom 0x6 word. 4 0 ro reserved 3 0 ro pme clock when this bit is a ?1?, it indicates that the function relies on the presence of the pci clock for pme# oper ation. when this bit is a ?0?, it indicates that no pci clock is required for the function to generate pme#. the value of this bit is loaded fr om the pme_ck bit in the eeprom 0x6 word. 2 - 0 0 ro power management pci version the value of this bit is loaded from the pme_ver[2:0] bits in the eeprom 0x6 word. wakeup frame control register (offset 0x021a): wfcr this register holds control information programmed by the cpu to control the transmit module function. bit default r/w description 15 - 8 0x00 ro reserved 7 0 rw mprxe magic packet rx enable when set, it enables the magic packet pattern detection. when reset, the magic packet pattern detection is disabled. 6 - 4 0x0 ro reserved 3 0 rw wf3e wake up frame 3 enable when set, it enables the wake up frame 3 pattern detection. when reset, the wake up frame pattern detection is disabled. 2 0 rw wf2e wake up frame 2 enable when set, it enables the wake up frame 2 pattern detection. when reset, the wake up frame pattern detection is disabled. 1 0 rw wf1e wake up frame 1 enable when set, it enables the wake up frame 1 pattern detection. when reset, the wake up frame pattern detection is disabled. 0 0 rw wf0e wake up frame 0 enable when set, it enables the wake up frame 0 pattern detection. when reset, the wake up frame pattern detection is disabled.
micrel, inc. ksz8841-pmql october 2007 48 m9999-100407-1.5 wakeup frame 0 crc0 register (offset 0x0220): wf0crc0 this register contains the expected crc values of the wake up frame 0 pattern. the value of the crc calculat ed is based on the ieee 802.3 ethe rnet standard, taken over the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf0crc0 wake up frame 0 crc (lower 16 bits) the expected crc value of a wake up frame 0 pattern. wakeup frame 0 crc1 register (offset 0x0222): wf0crc1 this register contains the expected crc values of the wake up frame 0 pattern. the value of the crc calculat ed is based on the ieee 802.3 ethe rnet standard, taken over the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf0crc1 wake up frame 0 crc (upper 16 bits) the expected crc value of a wake up frame 0 pattern. wakeup frame 0 byte mask 0 register (offset 0x0224): wf0bm0 this register contains the first 16 bytes mask values of t he wake up frame 0 pattern. setting bit 0 selects the first byte of the wake up frame 0; setting bit 15 select s the 16th byte of the wake up frame 0. bit default r/w description 15 - 0 -- rw wf0bm0 wake up frame 0 byte mask 0 the first 16 bytes mask of a wake up frame 0 pattern. wakeup frame 0 byte mask 1 register (offset 0x0226): wf0bm1 this register contains the next 16 bytes mask values of t he wake up frame 0 pattern. setting bit 0 selects the 17th byte of the wake up frame 0; setting bit 15 select s the 32nd byte of the wake up frame 0. bit default r/w description 15 - 0 -- rw wf0bm1 wake up frame 0 byte mask 1 the next 16 bytes mask covering bytes 17 to 32 of a wake up frame 0 pattern. wakeup frame 0 byte mask 2 register (offset 0x0228): wf0bm2 this register contains the next 16 byte s mask values of the wake up frame 0 pa ttern. setting bit 0 selects the 33rd byte of the wake up frame 0; setting bit 15 select s the 48th byte of the wake up frame 0. bit default r/w description 15 - 0 -- rw wf0bm2 wake up frame 0 byte mask 2 the next 16 bytes mask covering bytes 33 to 48 of a wake up frame 0 pattern.
micrel, inc. ksz8841-pmql october 2007 49 m9999-100407-1.5 wakeup frame 0 byte mask 3 register (offset 0x022a): wf0bm3 this register contains the last 16 byte s mask values of the wake up frame 0 pattern. setting bit 0 selects the 49th byte of the wake up frame 0; setting bit 15 select s the 64th byte of the wake up frame 0. bit default r/w description 15 - 0 -- rw wf0bm2 wake up frame 0 byte mask 3 the last 16 bytes mask covering bytes 49 to 64 of a wake up frame 0 pattern. wakeup frame 1 crc0 register (offset 0x0230): wf1crc0 this register contains the expected crc values of the wake up frame 1 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf1crc0 wake up frame 1 crc (lower 16 bits) the expected crc value of a wake up frame 1 pattern. wakeup frame 1 crc1 register (offset 0x0232): wf1crc1 this register contains the expected crc values of the wake up frame 1 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf1crc1 wake up frame 1 crc (upper 16 bits) the expected crc value of a wake up frame 1 pattern. wakeup frame 1 byte mask 0 register (offset 0x0234): wf1bm0 this register contains the first 16 bytes mask values of t he wake up frame 1 pattern. setting bit 0 selects the first byte of the wake up frame 1; setting bit 15 select s the 16th byte of the wake up frame 1. bit default r/w description 15 - 0 -- rw wf1bm0 wake up frame 1 byte mask 0 the first 16 bytes mask of a wake up frame 1 pattern. wakeup frame 1 byte mask 1 register (offset 0x0236): wf1bm1 this register contains the next 16 bytes mask values of t he wake up frame 1 pattern. setting bit 0 selects the 17th byte of the wake up frame 1; setting bit 15 select s the 32nd byte of the wake up frame 1. bit default r/w description 15 - 0 -- rw wf1bm1 wake up frame 1 byte mask 1 the next 16 bytes mask covering bytes 17 to 32 of a wake up frame 1 pattern.
micrel, inc. ksz8841-pmql october 2007 50 m9999-100407-1.5 wakeup frame 1 byte mask 2 register (offset 0x0238): wf1bm2 this register contains the next 16 byte s mask values of the wake up frame 1 pa ttern. setting bit 0 selects the 33rd byte of the wake up frame 1; setting bit 15 select s the 48th byte of the wake up frame 1. bit default r/w description 15 - 0 -- rw wf1bm2 wake up frame 1 byte mask 2 the next 16 byte mask covering bytes 33 to 48 of a wake up frame1 pattern. wakeup frame 1 byte mask 3 register (offset 0x023a): wf1bm3 this register contains the last 16 byte s mask values of the wake up frame 1 pattern. setting bit 0 selects the 49th byte of the wake up frame 1; setting bit 15 select s the 64th byte of the wake up frame 1. bit default r/w description 15 - 0 -- rw wf1bm2 wake up frame 1 byte mask 3 the last 16 bytes mask covering bytes 49 to 64 of a wake up frame 1 pattern. wakeup frame 2 crc0 register (offset 0x0240): wf2crc0 this register contains the expected crc values of the wake up frame 2 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf2crc0 wake up frame 2 crc (lower 16 bits) the expected crc value of a wake up frame 2 pattern. wakeup frame 2 crc1 register (offset 0x0242): wf2crc1 this register contains the expected crc values of the wake up frame 2 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf2crc1 wake up frame 2 crc (upper 16 bits) the expected crc value of a wake up frame 2 pattern. wakeup frame 2 byte mask 0 register (offset 0x0244): wf2bm0 this register contains the first 16 bytes mask values of t he wake up frame 2 pattern. setting bit 0 selects the first byte of the wake up frame 2; setting bit 15 select s the 16th byte of the wake up frame 2. bit default r/w description 15 - 0 -- rw wf2bm0 wake up frame 2 byte mask 0 the first 16 byte mask of a wake up frame 2 pattern.
micrel, inc. ksz8841-pmql october 2007 51 m9999-100407-1.5 wakeup frame 2 byte mask 1 register (offset 0x0246): wf2bm1 this register contains the next 16 bytes mask values of t he wake up frame 2 pattern. setting bit 0 selects the 17th byte of the wake up frame 2; setting bit 15 select s the 32nd byte of the wake up frame 2. bit default r/w description 15 - 0 -- rw wf2bm1 wake up frame 2 byte mask 1 the next 16 bytes mask covering bytes 17 to 32 of a wake up frame 2 pattern. wakeup frame 2 byte mask 2 register (offset 0x0248): wf2bm2 this register contains the next 16 byte s mask values of the wake up frame 2 pa ttern. setting bit 0 selects the 33rd byte of the wake up frame 2; setting bit 15 select s the 48th byte of the wake up frame 2. bit default r/w description 15 - 0 -- rw wf2bm2 wake up frame 2 byte mask 2 the next 16 bytes mask covering bytes 33 to 48 of a wake up frame 2 pattern. wakeup frame 2 byte mask 3 register (offset 0x024a): wf2bm3 this register contains the last 16 byte s mask values of the wake up frame 2 pattern. setting bit 0 selects the 49th byte of the wake up frame 2; setting bit 15 select s the 64th byte of the wake up frame 2. bit default r/w description 15 - 0 -- rw wf2bm2 wake up frame 2 byte mask 3 the last 16 bytes mask covering bytes 49 to 64 of a wake up frame 2 pattern. wakeup frame 3 crc0 register (offset 0x0250): wf3crc0 this register contains the expected crc values of the wake up frame 3 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf3crc0 wake up frame 3 crc (lower 16 bits) the expected crc value of a wake up frame 3 pattern. wakeup frame 3 crc1 register (offset 0x0252): wf3crc1 this register contains the expected crc values of the wake up frame 3 pattern. the value of the crc calculat ed is based on the ieee 802.3 ether net standard, it is taken ov er the bytes specified in the wake up byte mask registers. bit default r/w description 15 - 0 -- rw wf3crc1 wake up frame 3 crc (upper 16 bits) the expected crc value of a wake up frame 3 pattern.
micrel, inc. ksz8841-pmql october 2007 52 m9999-100407-1.5 wakeup frame 3 byte mask 0 register (offset 0x0254): wf3bm0 this register contains the first 16 bytes mask values of t he wake up frame 3 pattern. setting bit 0 selects the first byte of the wake up frame 3; setting bit 15 select s the 16th byte of the wake up frame 3. bit default r/w description 15 - 0 -- rw wf3bm0 wake up frame 3 byte mask 0 the first 16bytes mask of a wake up frame 3 pattern. wakeup frame 3 byte mask 1 register (offset 0x0256): wf3bm1 this register contains the next 16bytes mask values of the wake up frame 3 pattern. setting bit 0 selects the 17th byte of the wake up frame 3; setting bit 15 select s the 32nd byte of the wake up frame 3. bit default r/w description 15 - 0 -- rw wf3bm1 wake up frame 3 byte mask 1 the next 16bytes mask covering bytes 17 to 32 of a wake up frame 3 pattern. wakeup frame 3 byte mask 2 register (offset 0x0258): wf3bm2 this register contains the next 16bytes ma sk values of the wake up frame 3 pattern. setting bit 0 selects the 33rd byte of the wake up frame 3; setting bit 15 select s the 48th byte of the wake up frame 3. bit default r/w description 15 - 0 -- rw wf3bm2 wake up frame 3 byte mask 2 the next 16bytes mask covering bytes 33 to 48 of a wake up frame 3 pattern. wakeup frame 3 byte mask 3 register (offset 0x025a): wf3bm3 this register contains the last 16bytes mask values of t he wake up frame 3 pattern. setting bit 0 selects the 49th byte of the wake up frame 3; setting bit 15 select s the 64th byte of the wake up frame 3. bit default r/w description 15 - 0 -- rw wf3bm2 wake up frame 3 byte mask 3 the last 16 bytes mask covering bytes 49 to 64 of a wake up frame 3 pattern. chip id and enable register (offset 0x0400): cider this register contains the chip id , and the chip enables control. bit default r/w description 15-8 0x88 ro family id chip family id 7-4 0x05 ro chip id 0x05 is assigned to ksz8841-pmql 3-1 000 ro revision id 0 - rw start controller 1 = start the chip operation 0 = stop the chip operation
micrel, inc. ksz8841-pmql october 2007 53 m9999-100407-1.5 chip global control register (offset 0x040a): cgcr this register contains the global control for the chip function. bit default r/w description 15 0 rw ledsel1 see description for bit 9. 14-10 reserved rw reserved 9 0 rw ledsel0 the two register bits ledsel1 and ledsel0, are used to select the led mode. the led indicators, are defined as below: [ledsel1, ledsel0] [0, 0] [0, 1] p1led3 ------ ------ p1led2 link/act 100link/act p1led1 full_dpx/col 10link/act p1led0 speed full_dpx [ledsel1, ledsel0] [1, 0] [1, 1] p1led3 act ------ p1led2 link ------ p1led1 full_dpx/col ------ p1led0 speed ------ 8-0 0 rw reserved indirect access control register (offset 0x04a0): iacr this register contains the i ndirect control for the mib coun ter. write iacr will actually tr igger a command. read or write access is determined by this register bit 12. bit default r/w description 15-13 000 rw reserved 12 0 rw read high. write low 1 = read cycle 0 = write cycle 11-10 00 rw table select 11 = mib counter selected 9-0 0x000 rw indirect address bit 9-0 of indirect address note : (1) write iacr will actually trigger a command. read or write access is determined by register bit 12.
micrel, inc. ksz8841-pmql october 2007 54 m9999-100407-1.5 indirect access data register 1 (offset 0x04a2): iadr1 this register contains the indi rect data for the chip function. bit default r/w description 15-8 0x00 ro reserved 7 0 ro cpu read status only for dynamic and statistics counter reads. 1 = read is still in progress 0 = read has completed 6-3 0x0 ro reserved 2-0 000 ro reserved indirect access data register 2 (offset 0x04a4): iadr2 this register contains the indi rect data for the chip function. bit default r/w description 15-0 0x0000 rw indirect data bit 47-32 of indirect data indirect access data register 3 (offset 0x04a6): iadr3 this register contains the indi rect data for the chip function. bit default r/w description 15-0 0x0000 rw reserved indirect access data register 4 (offset 0x04a8): iadr4 this register contains the indi rect data for the chip function. bit default r/w description 15-0 0x0000 rw indirect data bit 15-0 of indirect data indirect access data register 5 (offset 0x04aa): iadr5 this register contains the indi rect data for the chip function. bit default r/w description 15-0 0x0000 rw indirect data bit 31-16 of indirect data reserved (offset 0x04c0-0x04cf)
micrel, inc. ksz8841-pmql october 2007 55 m9999-100407-1.5 phy 1 mii register basic control register (offset 0x04d0): p1mbcr this register contains the mii regi ster control for the chip function. bit default r/w description is the same as 15 0 ro soft reset not supported 14 0 rw reserved. 13 0 rw force 100 1 = force 100 mbps if an is disabled (bit12) 0 = force 10 mbps if an is disabled (bit12) p1cr4, bit 6 12 1 rw an enable 1 = auto-negotiation enabled 0 = auto-negotiation disabled p1cr4, bit 7 11 0 rw power down 1 = power down 0 = normal operation p1cr4, bit 11 10 0 ro isolate not supported 9 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p1cr4, bit 13 8 0 rw force full duplex 1 = force full duplex if an is disabled (bit12) 0 = force half duplex if an is disabled (bit12) p1cr4, bit 5 7 0 ro reserved 6 0 ro reserved 5 0 r/w hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p1sr, bit 15 4 0 rw force mdix 1 = force mdix 0 = normal operation p1cr4, bit 9 3 0 rw disable mdix 1 = disable auto mdix 0 = normal operation p1cr4, bit 10 2 0 rw disable far end fault 1 = disable far end fault detection 0 = normal operation p1cr4, bit 12 1 0 rw disable transmit 1 = disable transmit 0 = normal operation p1cr4, bit 14 0 0 rw disable led 1 = disable led 0 = normal operation p1cr4, bit 15
micrel, inc. ksz8841-pmql october 2007 56 m9999-100407-1.5 phy 1 mii register basic status re gister (offset 0x04d2): p1mbsr this register contains the mii regi ster control for the chip function. bit default r/w description is the same as 15 0 ro t4 capable 1 = 100 base-t4 capable 0 = not 100 baset4 capable 14 1 ro 100 full capable 1 = 100basetx full duplex capable 0 = not 100basetx full duplex capable always 1 13 1 ro 100 half capable 1 = 100basetx half duplex capable 0 = not 100basetx half duplex capable always 1 12 1 ro 10 full capable 1 = 10baset full duplex capable 0 = not 10baset full duplex capable always 1 11 1 ro 10 half capable 1 = 10baset half duplex capable 0 = not 10baset half duplex capable always 1 10-7 0 ro reserved 6 0 ro preamble suppressed not supported 5 0 ro an complete 1 = auto-negotiation complete 0 = auto-negotiation not completed p1sr, bit 6 4 0 ro far end fault 1 = far end fault detected 0 = no far end fault detected p1sr, bit 8 3 1 ro an capable 1 = auto-negotiation capable 0 = not auto-negotiation capable p1cr4, bit 7 2 0 ro link status 1 = link is up 0 = link is down p1sr, bit 5 1 0 ro reserved 0 0 ro extended capable 1 = extended register capable 0 = not extended register capable phy 1 phyid low register (offset 0x04d4): phy1ilr this register contains the phy id (low) for the chip function. bit default r/w description 15-0 0x1430 ro phyid low low order phyid bits
micrel, inc. ksz8841-pmql october 2007 57 m9999-100407-1.5 phy 1 phyid high register (offset 0x04d6): phy1ihr this register contains the phy id (high) for the chip function. bit default r/w description 15-0 0x0022 ro phyid high high order phyid bits phy 1 auto-negotiation advertisemen t register (offset 0x04d8): p1anar this register contains the auto-negotiati on advertisement for the chip function. bit default r/w description is the same as 15 0 ro next page not supported 14 0 ro reserved 13 0 ro remote fault not supported 12-11 0 ro reserved 10 1 rw pause (follow control capability) 1 = advertise pause ability 0 = do not advertise pause ability p1cr4, bit 4 9 0 rw reserved 8 1 rw adv 100 full 1 = advertise 100 full duplex ability 0 = do not advertise 100 full duplex ability p1cr4, bit 3 7 1 rw adv 100 half 1 = advertise 100 half duplex ability 0 = do not advertise 100 half duplex ability p1cr4, bit 2 6 1 rw adv 10 full 1 = advertise 10 full duplex ability 0 = do not advertise 10 full duplex ability p1cr4, bit 1 5 1 rw adv 10 half 1 = advertise 10 half duplex ability 0 = do not advertise 10 half duplex ability p1cr4, bit 0 4-0 0_0001 ro selector field 802.3 phy 1 auto-negotiation link partner ab ility register (offset 0x04da): p1anlpr this register contains the auto-negotiation link partner ab ility for the chip function. bit default r/w description is the same as 15 0 ro next page not supported 14 0 ro lp ack not supported 13 0 ro remote fault not supported 12-11 0 ro reserved
micrel, inc. ksz8841-pmql october 2007 58 m9999-100407-1.5 bit default r/w description is the same as 10 0 ro pause link partner pause capability p1sr, bit 4 9 0 ro reserved 8 0 ro adv 100 full link partner 100 full capability p1sr, bit 3 7 0 ro adv 100 half link partner 100 half capability p1sr, bit 2 6 0 ro adv 10 full link partner 10 full capability p1sr, bit 1 5 0 ro adv 10 half link partner 10 half capability p1sr, bit 0 4-0 0_0000 ro reserved phy1 linkmd control/status (offset 0x04f0): p1vct this register contains the link md control and status of phy 1: bit default r/w description is the same as 15 0 rw sc (self-clear) vct_enable 1 = the cable diagnostic test is enabled. it?ll be self-cleared after vct test is done 0 = it indicates the cable diagnostic test is completed and the status information is valid for read p1scslmd, bit 12 14 - 13 0 ro vct_result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p1scslmd, bit 14-13 12 - ro vct 10m short 1 = less than 10 meter short p1scslmd, bit 15 11 - 9 0 ro reserved 8 - 0 0 ro vct_fault_count distance to the fault. the distance is approximately 0.4m x vct_fault_count p1scslmd, bits 8-0 phy1 special control/status regist er (offset 0x04f2): p1phyctrl this register contains the contro l and status information of phy1: bit default r/w description is the same as 15 - 6 0 ro reserved 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed 0 = polarity is not reversed p1sr, bit 13
micrel, inc. ksz8841-pmql october 2007 59 m9999-100407-1.5 bit default r/w description is the same as 4 0 ro mdix status (mdix_st) 1 = mdix 0 = mdi p1sr, bit 7 3 0 rw force link (force_lnk) 1 = force link pass 0 = normal operation p1scslmd, bit 11 2 1 rw power saving (pwrsave) 1 = disable 0 = enable power saving p1scslmd, bit 10 1 0 rw remote loopback (rlb) 1 = loop back at pmd/pma of port?s phy (rxp1/rxm1 -> txp1/txm1) 0 = normal operation. p1scslmd, bit 9 0 0 rw reserved reserved (offset 0x04f8 - 0x04fa) bit default r/w description 15-0 0x0000 ro reserved port 1 phy special control/status, linkmd (offset 0x0510): p1scslmd this register contains the port linkmd control register for the chip function. bit default r/w description is the same as 15 0 ro vct 10m short less than 10 meter short p1vct, bit 12 14-13 0 ro vct result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test is failed p1vct, bits 14 - 13 12 0 rw sc (self - clear) vct enable 1 = the cable diagnostic test is enabled. it?ll be self-cleared after vct test is done 0 = it indicates the cable diagnostic test is completed and the status information is valid for read p1vct, bit 15 11 0 rw force link 1 = force link pass 0 = normal operation p1phyctrl, bit 3 10 1 rw power saving 1 = disable 0 = enable power saving p1phyctrl, bit 2
micrel, inc. ksz8841-pmql october 2007 60 m9999-100407-1.5 bit default r/w description is the same as 9 0 rw remote loopback 1 = loop back at pmd/pma of port?s phy (rxp1/rxm1 -> txp1/txm1) 0 = normal operation. p1phyctrl, bit 1 8-0 0x000 ro vct fault count distance to the fault. the distance is approximately 0.4m x vct_fault_count p1vct, bits 8-0 port 1 control register 4 (offset 0x0512): p1cr4 this register contains the global per port control for the chip function. bit default r/w description is the same as 15 0 rw led off 1 = turn off all port?s leds (led1_3, led1_2, led1_1, led1_0. these pins will be driven high if this bit is set to one 0 = normal operation p1mbcr, bit 0 14 0 rw txids 1 = disable port?s transmitter 0 = normal operation p1mbcr, bit 1 13 0 rw restart an 1 = restart auto-negotiation 0 = normal operation p1mbcr, bit 9 12 0 rw disable far end fault 1 = disable far end fault detection & pattern transmission. 0 = enable far end fault detection & pattern transmission. p1mbcr, bit 2 11 0 rw power down 1 = power down 0 = normal operation p1mbcr, bit 11 10 0 rw disable auto mdi/mdix 1 = disable auto mdi/mdix function 0 = enable auto mdi/mdix function p1mbcr, bit 3 9 0 rw force mdix 1 = if auto mdi/mdix is disabled, force phy into mdix mode 0 = do not force phy into mdix mode p1mbcr, bit 4 8 0 reserved p1mbcr, bit 14 7 1 rw auto negotiation enable 1 = auto negotiation is enable 0 = disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. p1mbcr, bit 12 6 0 rw force speed 1 = force 100bt if an is disabled (bit 7) p1mbcr, bit 13
micrel, inc. ksz8841-pmql october 2007 61 m9999-100407-1.5 bit default r/w description is the same as 0 = force 10bt if an is disabled (bit 7) 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. p1mbcr, bit 9 4 1 rw advertised flow control capability 1 = advertise flow control (pause) capability 0 = suppress flow control (pause) capability from transmission to link partner p1anar, bit 4 3 1 rw advertised 100bt ful l duplex capability 1 = advertise 100bt full duplex capability 0 = suppress 100bt full duplex capability from transmission to link partner p1anar, bit 3 2 1 rw advertised 100bt ha lf duplex capability 1 = advertise 100bt half duplex capability 0 = suppress 100bt half duplex capability from transmission to link partner p1anar, bit 2 1 1 rw advertised 10bt ful l duplex capability 1 = advertise 10bt full duplex capability 0 = suppress 10bt full duplex capability from transmission to link partner p1anar, bit 1 0 1 rw advertised 10bt half duplex capability 1 = advertise 10bt half duplex capability 0 = suppress 10bt half duplex capability from transmission to link partner p1anar, bit 0 port 1 status register (offset 0x0514): p1sr this register contains the global per port status for the chip function. bit default r/w description is the same as 15 0 rw hp_mdix 1 = hp auto mdix mode 0 = micrel auto mdix mode p1mbcr, bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed 0 = polarity is not reversed p1phyctrl, bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive 11 0 ro transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 10 0 ro operation speed 1 = link speed is 100mbps
micrel, inc. ksz8841-pmql october 2007 62 m9999-100407-1.5 bit default r/w description is the same as 0 = link speed is 10mbps 9 0 ro operation duplex 1 = link duplex is full 0 = link duplex is half 8 0 ro far end fault 1 = far end fault status detected 0 = no far end fault status detected p1mbsr, bit 4 7 0 ro mdix status 1 = mdix 0 = mdi p1phyctrl, bit 4 6 0 ro an done 1 = an done 0 = an not done p1mbsr, bit 5 5 0 ro link good 1 = link good 0 = link not good p1mbsr, bit 2 4 0 ro partner flow control capability 1 = link partner flow control (pause) capable 0 = link partner not flow control (pause) capable p1anlpr, bit 10 3 0 ro partner 100bt full duplex capability 1 = link partner 100bt full duplex capable 0 = link partner not 100bt full duplex capable p1anlpr, bit 8 2 0 ro partner 100bt half duplex capability 1 = link partner 100bt half duplex capable 0 = link partner not 100bt half duplex capable p1anlpr, bit 7 1 0 ro partner 10bt full duplex capability 1 = link partner 10bt full duplex capable 0 = link partner not 10bt full duplex capable p1anlpr, bit 6 0 0 ro partner 10bt half duplex capability 1 = link partner 10bt half duplex capable 0 = link partner not 10bt half duplex capable p1anlpr, bit 5 reserved (offset 0x0516 ? 0x0560) bit default r/w description 15 - 0 0x0000 ro reserved
micrel, inc. ksz8841-pmql october 2007 63 m9999-100407-1.5 mib (management information base) counters the ksz8841-pmql provides 32 mib counters to monitor t he port activity for network management. the mib counters are formatted as shown in table 4. bit name r/w description default 31 overflow ro 1 = counter overflow. 0 = no counter overflow. 0 30 count valid ro 1 = counter value is valid. 0 = 0 counter value is not valid. 0 29-0 counter values ro counter value 0 table 4. format of port mib counters the port mib counters are read using indirect memory ac cess. the base address offsets is 0x00 and address ranges is 0x00-0x1f as shown in table 5. the port mib counters read/write functions use access control register iacr (0 x04a0) bit 12. the base address offset and address range for port 1 is 0x00 and range is (0x00-0x1f) that can be changed in register iacr (0x04a0) bits[9:0]. the data of mib counters are from the indirect access da ta register iadr4 (0x04a8) and iadr5 (0x04aa) based on table 4. offset counter name description 0x0 (base address) rxbyte rx octet count including bad packets. 0x1 reserved. do not write to this register. 0x2 rxundersizepkt rx undersize packets w/ good crc. 0x3 rxfragments rx fragment packets w/ b ad crc, symbol errors or alignment errors. 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 or 1522 bytes). 0x5 rxjabbers rx packets longer than 1522 bytes w/ either crc errors, alignment errors, or symbol errors (depe nds on max packet size setting). 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x9 rxcontrol8808pkts number of mac control frames received by a port with 88-08h in ethertype field. 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with ethertype (88-08h), da, cont rol opcode (00-01), data length (64b min), and a valid crc. 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast packets). 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packets or valid broadcast packets). 0xd rxunicast rx good unicast packets. 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length. 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length. 0x10 rx128to255octets total rx packets (bad packets inc luded) that are between 128 and 255 octets in length. 0x11 rx256to511octets total rx packets (bad packets inc luded) that are between 256 and 511
micrel, inc. ksz8841-pmql october 2007 64 m9999-100407-1.5 offset counter name description octets in length. 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length. 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x14 txbyte tx good octet count, including pause packets. 0x15 reserved. do not write to this register. 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet. 0x17 txpausepkts number of pause frames transmitted by a port. 0x18 txbroadcastpkts tx good broadcast packets (not including error broadcast or valid multicast packets). 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets). 0x1a txunicastpkts tx good unicast packets. table 5. port 1?s mib counters indirect memory offsets example: mib counter read (read ?rx64octets? counter at indirect address offset 0x0e) write to reg. iacr with 0x1c0e (set indirect address and trigger a read mib counters operation) then: read reg. iadr5 (mib counter value 31-16) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, re start (reread) from this register read reg. iadr4 (mib counter value 15-0) additional mib information in the heaviest condition, the byte counter will overflow in 2 minutes. it is recommended that t he software read all the counters at least every 30 seconds. mib counters are designed as ?read clear?. that is, these counters will be cleared after they are read.
micrel, inc. ksz8841-pmql october 2007 65 m9999-100407-1.5 absolute maximum ratings (1) supply voltage (v ddatx , v ddarx , v ddio ) ........................... ?0.5v to +4.0v input voltage (all input s). ............................. ?0.5v to +5.0v output voltage (all outpu ts) ......................... ?0.5v to +4.0v lead temperature (solde ring, 10sec .) ....................... 270c storage temperature (t s ) .........................?55c to +150c operating ratings (2) supply voltage (v ddatx , v ddarx , v ddio )...................... +3.1v to +3.5v ambient temperature (t a ) ....................... 0c to +70c junction temperature (t j ) .................................. 125c package thermal resistance (3) pqfp ( ja ) no air fl ow........................ 42.91c/w pqfp ( jc ) no air flow .......................... 19.6c/w electrical characteristics (4) symbol parameter condition min typ max units supply current 100base-tx operation (all ports @ 100% utilization) i ddxio 100base-tx (analog core + digital core + transceiver + digital i/o) v ddatx , v ddarx , v ddio = 3.3v 100 ma 10base-tx operation (all ports @ 100% utilization) i ddxio 100base-tx (analog core + digital core + transceiver + digital i/o) v ddatx , v ddarx , v ddio = 3.3v 85 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ v ddio ?10 10 a ttl outputs v oh output high voltage i oh = ?8ma 2.4 v v ol output low voltage i ol = 8ma 0.4 v i oz output tri-state leakage 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v ddatx = 3.3v only v o peak differential output voltage 100 ? termination on the differential output. 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output. 2 % rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns t r , t f overshoot 5 % reference voltage of i set 0.5 v v set output jitter peak to peak 0.7 1.4 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv 10base-t transmit (measured differentially after 1:1 transformer) v ddatx = 3.3v only peak differential output voltage 100 ? termination on the differential output. 2.4 v v p jitter added 100 ? termination on the differential output. 1.8 3.5 ns
micrel, inc. ksz8841-pmql october 2007 66 m9999-100407-1.5 notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than those listed in the table above may cause permanent damage to the device. operation of the device at these or any other conditions above those specif ied in the operating sections of this specification is not implied. maximum conditions for ex tended periods may affect reliability. unused inputs must always be tied to an appropr iate logic voltage level. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground to vdd) 3. no (hs) heat spreader in this pack age. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. a single port?s trans former consumes an additional 45m a at 3.3v for 100base-t and 7 0ma at 3.3v for 10base-t.
micrel, inc. ksz8841-pmql october 2007 67 m9999-100407-1.5 timing diagrams for pci timing, please refer to pci specification version 2.2. eeprom timing eecs eesk eedo eedi *1 start bit hight-z d15 d14 d13 d1 d0 11 0 an a0 1 *1 ts th figure 7. eeprom read cycle timing diagram timing parameter description min typ max unit t cyc clock cycle 4000 ns t s setup time 20 ns t h hold time 20 ns table 6. eeprom timing parameters
micrel, inc. ksz8841-pmql october 2007 68 m9999-100407-1.5 auto negotiation timing tx+/tx- tx+/tx- flp burst flp burst t flpw t btb clock pulse clock pulse data pulse data pulse t pw t pw t ctd t ctc figure 8. auto-negotiation timing timing parameter description min typ max unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per burst 17 33 table 7. auto negotiation parameters
micrel, inc. ksz8841-pmql october 2007 69 m9999-100407-1.5 reset timing as long as the stable supply voltages to reset high timing (minimum of 10ms) are met, there is no power-sequencing requirement for the ksz8841-pmql supply voltages (3.3v). the reset timing requirement is summarized in the figure 7 and table 8. supply v oltage rst_n t sr figure 9. reset timing symbol parameter min max unit t sr stable supply voltages to reset high 10 ms table 8. reset timing parameters
micrel, inc. ksz8841-pmql october 2007 70 m9999-100407-1.5 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode choke is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min) 350 h 100mv, 100khz, 8ma leakage inductance (max) 0.4 h 1mhz (min) inter-winding capacitance (max) 12pf d.c. resistance (max) 0.9 ? insertion loss (max) 1.0db 0mhz ? 65mhz hipot (min) 1500vrms table 9. transformer selection criteria the following transformer vender provide comp atible transformers for micrel?s device: magnetic manufacturer part number auto mdi-x number of port pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 bel fuse s558-5999-u7 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 tdk (mag jack) tla-6t718 yes 1 table 10. qualified single port magnetics selection of reference crystal characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 25 ? table 11. typical reference crystal characteristics
micrel, inc. ksz8841-pmql october 2007 71 m9999-100407-1.5 package information figure 10. 128-pin pqfp package
micrel, inc. ksz8841-pmql october 2007 72 m9999-100407-1.5 acronyms and glossary bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arri ves at its proper destination. cmos complementary metal oxide semiconductor a common semiconductor manufacturing technique in which positive and negative types of transistors are com bined to form a current gate that in turn forms an effective means of c ontrolling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmission errors . crc for ethernet is 32 bits long. cut-through switch a switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. a cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. cut-through switches do not store the packet. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled independently of the cpu. eeprom electronically erasable programmable read- only memory a design in which memory on a chip can be erased by exposing it to an electrical charge. eisa extended industry standard architecture a bus architecture designed for pcs using 80x86 processors, or an intel 80386, 80486 or pentium micropr ocessor. eisa buses are 32 bits wide and support multiprocessing . emi electro-magnetic interference a naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades t he electromagnetic field of another device by coming into proximity with it. in computer technology, computer devices are susceptible to emi bec ause electromagnetic fields are a byproduct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame ident ifier. alternately is the filter identifier. igmp internet group management protocol the protocol defined by rfc 1112 for ip multicast transmissions. ipg inter-packet gap a time delay between successive data packets mandated by the network standard for protocol reasons. in ether net, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferred, and informati on in the gap can be discarded or additions inserted without impact on data integrity. isi inter-symbol interference t he disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at . jumbo packet a packet larger than the standard et hernet packet (1500 bytes). large packet sizes allow for more efficient use of bandwidth, lower overhead,
micrel, inc. ksz8841-pmql october 2007 73 m9999-100407-1.5 less processing, etc. mdi medium dependent interface an ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' mdi-x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null-modem, or crossover, cable. for 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi-x, the phy senses the correct tx and rx role s, eliminating any cable confusion. mib management information base the mib comprises the management portion of network devices. this can include things like monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. npvid non port vlan id the port vlan id value is used as a vlan reference. pll phase-locked loop an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communica tion signal is locked on a specific frequency and can also be used to gener ate, modulate, and demodulate a signal and divide a frequency. pme power management event an occurrence that affects the directi ng of power to different components of a system. qmu queue management unit manages packet traffic between mac/phy interface and the system host. the qmu has built-in packet memories for receive and transmit functions called txq (transmit queue) and rxq (receive queue). sa source address the address from which information has been sent. tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it takes for the signal -- or part of the signal -- to return. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere.
micrel, inc. ksz8841-pmql october 2007 74 m9999-100407-1.5 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life s upport appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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